SiC Switching Circuit Gate Driver Load Reduction
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Solution Overview
Problem
The existing inverter circuit using SiC devices faces increased load on the gate driver circuit due to the need to supply charge and discharge currents for capacitors used to control switching, leading to potential false triggering and increased switching losses.
Innovation Solution
A switching circuit design that includes a resistor and capacitor configuration between the control electrode and the gate driver circuit, with a second switching element connected between the control electrode and a low potential-side electrode, to reduce the load on the gate driver circuit and prevent false triggering by suppressing voltage rises between the gate and source.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a capacitor is inserted between the gate and source of the main switching element to prevent false triggering, then false triggering is suppressed, but the load on the gate driver circuit increases due to charge and discharge currents
Solution Approach 1:
The patent divides the capacitor charging/discharging function into two separate paths: one path through the gate driver circuit (for controlled switching) and another path through the parallel capacitor connected between drain and source (for suppressing voltage spikes). This segmentation reduces the burden on the gate driver circuit while maintaining false triggering prevention.
Solution Approach 2:
The patent introduces an intermediary capacitor connected between the drain and source terminals that acts as a mediator to suppress voltage spikes and prevent false triggering. This intermediary component handles the charge/discharge currents independently from the gate driver circuit, thereby reducing the gate driver's load while maintaining system reliability.
2Ease of operation
If charge and discharge currents are supplied from the gate driver circuit to control switching, then switching control is achieved, but output waveforms become blunt and switching speeds decrease
Solution Approach 1:
The patent segments the current paths by providing alternative routes for charge and discharge currents through the parallel capacitor and resistor network. This allows the gate driver to maintain control functionality while high-frequency switching currents bypass through the parallel components, preserving switching speed and waveform integrity.
Solution Approach 2:
The patent changes the electrical parameters of the circuit by adding parallel capacitance and resistance elements, which modifies the current distribution characteristics. This parameter change enables the gate driver to operate at lower current levels while maintaining effective switching control, thereby preventing waveform blunting and preserving switching speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the load on the gate driver circuit, prevents false triggering, and maintains high switching speeds by minimizing the burden on the gate driver circuit and avoiding blunting of output waveforms.
Implementation Method 1
includes a capacitor inserted between the gate and the source of a junction field effect transistor serving as a main switching element; and thus prevents false triggering by suppressing a rising change in the voltage between the gate and the source during a rise in the voltage between the drain and the source
Implementation Method 2
a resistor inserted between a control electrode of the first switching element and a control circuit configured to perform switching control on the first switching element
Data Source
AI summary
A switching circuit includes: a first switching element (Q1); a resistor (11) inserted between a control electrode (G) of the first switching element (Q1) and a control circuit (13) switching the first switching element (Q1); and a first capacitor (15) and a second switching element (14) connected in series between the control electrode (G) of the first switching element (Q1) and a low potential-side electrode (S) of the first switching element (Q1). A high potential-side electrode of the second switching element (14) is connected to the control electrode (G) of the first switching element (Q1). An electrode of the first capacitor (15) is connected to the low potential-side electrode (S) of the first switching element (Q1). A control electrode of the second switching element (14) is connected to an electrode of the resistor (11) connected to the control circuit (13).