SiC Semiconductor Terminal Stacked Parallel Plate Inductance Reduction
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Solution Overview
Problem
Conventional semiconductor devices with silicon carbide (SiC) materials face challenges in further increasing switching speed while suppressing surge voltage, as the limited facing area between positive and negative electrode terminals restricts the reduction of parasitic inductance and subsequent surge voltage.
Innovation Solution
The semiconductor device incorporates a configuration with multiple facing portions on the power supply terminals, allowing current to flow in opposite directions through specific portions, reducing parasitic inductance and thereby suppressing surge voltage while enhancing switching speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If switching speed is increased in SiC semiconductor devices, then switching loss is reduced, but surge voltage increases
Solution Approach 1:
The patent transitions from a conventional single-plane terminal arrangement to a three-dimensional stacked parallel plate configuration. The positive electrode terminal and negative electrode terminal are arranged in multiple stacked layers, creating parallel plate regions that extend in the vertical direction. This dimensional change increases the effective facing area between terminals, thereby reducing parasitic inductance and suppressing surge voltage while maintaining high switching speed.
Solution Approach 2:
The terminal structure is segmented into multiple stacked parallel plate regions rather than a single monolithic terminal. Each stacked layer pair forms an independent parallel plate region with its own facing area. This segmentation allows the total parasitic inductance to be distributed and reduced across multiple regions, effectively lowering the overall surge voltage while maintaining the high switching speed capability.
2Area of stationary object
If the facing area between positive and negative electrode terminals is increased, then parasitic inductance is reduced, but device complexity increases
Solution Approach 1:
The patent merges multiple terminal functions into a stacked parallel plate configuration where positive and negative electrode terminals are integrated in alternating layers. This merging approach increases the effective facing area without proportionally increasing the device footprint, as the terminals share the same spatial volume through vertical stacking. The integrated structure reduces parasitic inductance while maintaining manageable device complexity through efficient space utilization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces parasitic inductance and surge voltage, improving the reliability and switching speed of semiconductor devices beyond conventional limits.
Implementation Method 1
The first facing portion and the second facing portion are provided such that, upon application of a current, the current flows through the first facing portion and the second facing portion in a direction opposite to a direction in which the current flows through each of portions in the second power supply terminal that face the first facing portion and the second facing portion
Implementation Method 2
a current flows through one of these two stacked parallel plate regions in a direction opposite to a direction in which a current flows through the other of the stacked parallel plate regions, and thereby, the inductances in the positive electrode terminal and the negative electrode terminal decrease
Data Source
AI summary
A semiconductor device includes: a first power supply terminal; a second power supply terminal; an output terminal; a first switching element connected between the first power supply terminal and the output terminal; and a second switching element connected between the second power supply terminal and the output terminal. The first power supply terminal includes: a first facing portion; a second facing portion; and a third facing portion. The first facing portion and the second facing portion are provided such that, upon application of a current, the current flows through the first facing portion and the second facing portion in a direction opposite to a direction in which the current flows through each of portions in the second power supply terminal that face the first facing portion and the second facing portion.