Insulating Terminal Table for SiC Semiconductor Resin Crack Prevention
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Solution Overview
Problem
Wide band gap semiconductor devices, such as those using SiC and GaN, face reliability issues due to crack formation and separation of the sealing resin from the substrate during high-temperature operations, leading to reduced reliability.
Innovation Solution
A semiconductor device configuration with a front-surface electrode pattern on an insulating substrate, a back-surface electrode, and a sealing resin member, where an insulating terminal table with a conductive relay terminal is used to insulate the relay terminal from the front-surface electrode pattern, ensuring the same electric potential and preventing resin separation or crack formation during high-temperature operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If a semiconductor element operates at high temperatures, then the operating temperature range is improved, but crack formation on bonding material and separation of sealing resin occur
Solution Approach 1:
The patent applies equipotentiality by providing an insulating terminal table at a position with electric potential equivalent to the front-surface electrode pattern where the semiconductor element is bonded. This creates an equipotential region that prevents electrical stress concentration and associated thermal stress during high-temperature operation, thereby preventing crack formation on bonding material and separation of sealing resin while maintaining high operating temperatures.
2Power
If the withstand voltage is increased, then the electrical performance is improved, but the risk of electrical stress concentration is increased
Solution Approach 1:
The patent introduces an insulating terminal table as an intermediary component between the front-surface electrode pattern and the sealing resin. This intermediary structure provides electrical insulation and distributes electrical stress, preventing stress concentration at critical interfaces while maintaining high withstand voltage capability.
3Power
If the current density is increased, then the electrical performance is improved, but the thermal stress and electrical stress on wirings are increased
Solution Approach 1:
The insulating terminal table creates an equipotential region that distributes electrical stress uniformly across the bonding material and wirings. This prevents localized stress concentration that would otherwise occur at high current density interfaces, thereby maintaining wiring and bonding material strength even when operating at high current densities.
Data Source
AI summary
A semiconductor device includes: a semiconductor-element substrate in which a front-surface electrode pattern is formed on a surface of an insulating substrate and a back-surface electrode is formed on another surface; semiconductor elements affixed to the surface of the front-surface electrode pattern opposite the insulating substrate; and a sealing resin member which covers the semiconductor element and the semiconductor-element substrate, wherein at a position of the front-surface electrode pattern where the position has potential equivalent to that of the front-surface electrode pattern at a position where a semiconductor element is bonded, an insulating terminal table formed with a conductive relay terminal and an insulating member that insulates the relay terminal and the front-surface electrode pattern from each other are provided, and wiring from the semiconductor element to the outside is led out via the relay terminal.