SiC Termination Region Impurity Profile for Etching Margin
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Solution Overview
Problem
Conventional silicon carbide semiconductor device manufacturing methods have a narrow margin for etching the surface damage layer in termination regions, requiring precise control to achieve desired withstand voltage, which is challenging due to the formation of a Box type impurity concentration profile.
Innovation Solution
The method involves forming a silicon carbide semiconductor device with a termination region, including a JTE or FLR, where the impurity concentration peak is positioned deeper than 0.35 μm from the surface, allowing for a wider margin of etching by suppressing surface impurity concentration variations, thereby enabling the removal of the damage layer without significant impact on withstand voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If ion implantation is performed to form a JTE region with Box type impurity concentration profile, then the withstand voltage is improved, but the margin of etching amount becomes small requiring precise control
Solution Approach 1:
The patent changes the impurity concentration profile parameter from a Box type (uniform concentration) to a triangular type (gradually decreasing concentration from surface to peak). This parameter change in the impurity distribution allows the damage layer to be removed with a standard etching amount while maintaining the desired withstand voltage, eliminating the need for precise etching control.
2Strength
If multiple stage ion implantation is performed with varying implant energies, then the JTE region with desired withstand voltage is formed, but the manufacturing process complexity increases
Solution Approach 1:
The patent simplifies the manufacturing process by changing the implantation strategy from multiple stages with varying energies to a single stage or reduced stages. The triangular impurity concentration profile is achieved through optimized single-stage implantation parameters, reducing process complexity while maintaining the required withstand voltage performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enlarges the margin of etching, reducing the need for precise control and ensuring the desired withstand voltage is maintained, even with sacrificial oxidation alone, without the need for dry etching, thus preventing electric field concentration and enhancing manufacturing efficiency.
Implementation Method 1
forming a termination region including at least one of a JTE region and an FLR by impurity ion implantation in a surface portion of the silicon carbide semiconductor layer
Implementation Method 2
after the activation annealing, the damage layer must be removed by sacrificial oxidation or dry etching
Data Source
AI summary
In the manufacture of a silicon carbide semiconductor device having a termination region being a JTE region or FLR, the margin of the amount of etching for removing a damage layer formed in the surface of the termination region is enlarged. A silicon carbide semiconductor device has a termination region being a JTE (Junction Termination Extension) region or an FLR (Field Limiting Ring) at a termination of the semiconductor elements. The termination region is formed by one step of ion implantation in which the kind of impurity and the implant energy are fixed. In the impurity concentration profile of the termination region in the depth direction, the concentration peak in the shallowest position is in a position deeper than 0.35 μm from the surface, and the concentration in the surface portion is not more than one-tenth of the shallowest concentration peak.