SiC Trench Gate Structure for Threshold Voltage Aging Control
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Solution Overview
Problem
SiC semiconductor devices experience aging degradation of gate threshold voltage due to long-term use, which is linked to the impurity concentration of the contact region.
Innovation Solution
The SiC semiconductor device incorporates a contact region with a specific impurity concentration of not more than 1.0×10^20 cm^-3, and includes first and second conductivity type impurities where portions of the second conductivity type impurities are cancelled or compensated by the first conductivity type impurities, forming an Ohmic contact with the source region and a Schottky junction with the contact region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the contact region has high impurity concentration, then the electrical conductivity is improved, but the gate threshold voltage degrades due to aging
Solution Approach 1:
The patent applies parameter changes by precisely controlling the impurity concentration in the contact region to not more than 1.0×10^20 cm^-3, which is a specific parameter threshold. This parameter control resolves the contradiction by finding the optimal concentration level that prevents aging degradation while maintaining sufficient electrical conductivity for device operation.
Solution Approach 2:
The patent applies local quality by creating different impurity concentration zones within the semiconductor structure. The contact region has controlled low impurity concentration (≤1.0×10^20 cm^-3) while other regions like the source region and body region have different impurity concentrations optimized for their specific functions. This spatial differentiation of material properties resolves the contradiction by localizing the low-impurity condition specifically in the contact region to prevent aging without compromising overall device performance.
2Duration of action of stationary object
If the contact region impurity concentration is reduced, then aging degradation is suppressed, but the electrical conductivity may be compromised
Solution Approach 1:
The patent establishes a specific parameter threshold for impurity concentration (not more than 1.0×10^20 cm^-3) that balances two competing requirements: suppressing aging degradation while maintaining adequate electrical conductivity. This parameter optimization resolves the contradiction by identifying the precise concentration boundary where device lifetime is extended without sacrificing electrical performance.
Solution Approach 2:
The patent applies local quality by confining the low impurity concentration condition specifically to the contact region, while allowing other regions to have higher impurity concentrations optimized for their functions. This localized approach ensures that the contact region benefits from reduced aging degradation while the overall device maintains necessary electrical conductivity through appropriately doped source and body regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses the aging degradation of the gate threshold voltage, improving the stability and performance of the SiC semiconductor device over time.
Implementation Method 1
portions of the second conductivity type impurities are cancelled/compensated for by the first conductivity type impurities
Implementation Method 2
form an Ohmic contact with the source region
Implementation Method 3
form a Schottky junction with the contact region
Data Source
AI summary
An SiC semiconductor device includes an SiC semiconductor layer having a first main surface and a second main surface, a gate electrode embedded in a trench with a gate insulating layer, a source region of a first conductivity type formed in a side of the trench in a surface layer portion of the first main surface, a body region of a second conductivity type formed in a region at the second main surface side with respect to the source region in the surface layer portion of the first main surface, a drift region of the first conductivity type formed in a region at the second main surface side in the SiC semiconductor layer, and a contact region of the second conductivity type having an impurity concentration of not more than 1.0×1020 cm−3 and formed in the surface layer portion of the first main surface.