SiC Semiconductor Threshold Voltage Stability via Compressive Stress
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Solution Overview
Problem
Silicon carbide semiconductor devices experience time-dependent changes in threshold voltage when a negative bias is applied, particularly due to lattice mismatch and interface state formation between the semiconductor layer and the gate insulating film, leading to operational instability.
Innovation Solution
A semiconductor device structure incorporating a silicon carbide substrate with a drift layer, well regions, a gate insulating film, and a residual compressive stress layer formed on the source contact hole, which helps to reduce lattice mismatch and interface trap levels by applying compressive stress to separate the gate insulating film from the semiconductor surface, thereby stabilizing the threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a gate insulating film is formed on the silicon carbide semiconductor surface, then the device structure is completed, but lattice mismatch causes interface state formation leading to threshold voltage time variation
Solution Approach 1:
A residual compressive stress layer is introduced as an intermediary between the gate insulating film and the silicon carbide semiconductor surface. This intermediate layer serves as a buffer that compensates for lattice mismatch, preventing interface state formation while allowing the gate insulating film to maintain its insulating function.
Solution Approach 2:
The invention changes the physical parameter of stress in the intermediate layer to compressive stress, which specifically counteracts the tensile stress caused by lattice mismatch. By controlling the stress parameter in the intermediate layer, the interface quality is improved and threshold voltage stability is enhanced.
2Reliability
If the gate insulating film is directly formed on the semiconductor surface, then the device structure is simple, but lattice mismatch causes operational instability under negative bias
Solution Approach 1:
The residual compressive stress layer acts as a mediator that resolves the lattice mismatch issue without significantly complicating the device structure. This single additional layer provides the necessary stress compensation while maintaining structural simplicity.
Solution Approach 2:
By introducing a controllable stress parameter through the intermediate layer, the invention addresses operational stability without adding complex structural elements. The stress parameter can be adjusted during fabrication to optimize performance.
3Reliability
If no stress compensation is provided, then the manufacturing process is simple, but threshold voltage changes with time under negative bias
Solution Approach 1:
The invention incorporates stress as a controllable parameter in the manufacturing process. By forming the residual compressive stress layer with specific stress characteristics, threshold voltage stability is achieved through a relatively straightforward process extension that can be integrated into existing fabrication workflows.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively suppresses time variation in the threshold voltage, reducing it to minimal levels and enhancing the operational stability of silicon carbide semiconductor devices under negative bias conditions.
Implementation Method 1
a residual compressive stress layer formed on at least a side surface of the source contact hole, in which a compressive stress remains
Data Source
AI summary
A semiconductor device capable of suppressing time variation of a threshold voltage and a method of manufacturing the same. A semiconductor device according to the present invention comprises a drift layer formed on a semiconductor substrate, first well regions formed in a surface layer of the drift layer, being apart from one another, a gate insulating film formed, extending on the drift layer and each of the first well regions, a gate electrode selectively formed on the gate insulating film, a source contact hole penetrating through the gate insulating film and reaching the inside of each of the first well regions, and a residual compressive stress layer formed on at least a side surface of the source contact hole, in which a compressive stress remains.