SiC Power Transistor Structure for Low RSP at High Breakdown Voltage
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Solution Overview
Problem
Semiconductor materials like monocrystalline Si struggle to operate at high voltages and currents, and SiC transistors have higher specific on-state resistance (RSP) and face challenges in scaling to smaller dimensions.
Innovation Solution
The design incorporates a carrier accumulation region, buried shields, and a carrier distribution layer to reduce RSP, with multiple gate trench segments and a continuous gate trench to enhance current flow and simplify transistor design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SiC is used in transistors to operate at high voltages and currents, then the transistor can withstand high voltages and currents, but the specific on-state resistance (RSP) becomes higher than desired
Solution Approach 1:
The patent introduces a carrier accumulation region with higher dopant concentration specifically in the drift region where carriers need to accumulate, creating a localized high-conductivity path. This allows the bulk SiC material to maintain its high breakdown voltage properties while the localized region provides low on-state resistance through accumulated carriers.
Solution Approach 2:
The patent pre-accumulates carriers in the drift region through doping and electric field formation before the transistor is fully activated. This preliminary carrier accumulation reduces the time and voltage required to achieve low on-state resistance when the transistor switches on, effectively lowering the RSP before high current flow begins.
2Length of moving object
If transistors are scaled to smaller dimensions, then the transistor size is reduced, but it becomes challenging to maintain performance at high voltages and currents
Solution Approach 1:
The patent transitions from planar scaling to vertical structuring by introducing deep carrier accumulation regions and multi-layer doping profiles extending vertically through the drift region. This vertical dimension allows performance optimization without reducing lateral dimensions, maintaining high voltage capability while enabling smaller overall device footprint through efficient vertical current flow paths.
Solution Approach 2:
The patent employs composite doping structures combining regions of different dopant concentrations and types (n-type and p-type regions) within the SiC substrate. This composite approach creates optimized electric field distribution and carrier transport paths that maintain high voltage breakdown capability in scaled devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design reduces RSP and allows for smaller transistor dimensions while maintaining high breakdown voltage, improving operational efficiency and reliability under high voltage and current conditions.
Implementation Method 1
a carrier accumulation region having the first conductivity type
Implementation Method 2
a carrier distribution layer having the first conductivity type
Data Source
AI summary
An electronic device can include a substrate and a carrier accumulation region. In an implementation, the electronic device can further include a gap region, and a buried shield. The gap region is along a majority carrier flow path between substrate and the carrier accumulation region. In another implementation, the electronic device can further include a carrier distribution layer, a body region, and a body contact region. The body contact region has a second conductivity type and electrically couples the buried shield to the body region. The gap region can be along a majority carrier flow path between the carrier accumulation region and the carrier distribution layer. In a further implementation, the electronic device can include a gate member and an intermediate region between source regions. The gate member can include gate electrodes within gate trenches and an intermediate portion overlapping the intermediate region.