SiC Transistor Shielded Gate Trench
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Solution Overview
Problem
Silicon-carbide (SiC) based power transistors face challenges such as defects in the interface between SiC and gate dielectric due to thermal oxidation, leading to lower electron mobility and increased on-resistance, as well as uneven gate trench corners that result in higher electric fields and susceptibility to failure, making it difficult to achieve optimal avalanche breakdown properties.
Innovation Solution
A method involving the formation of a silicon-carbide semiconductor substrate with buried doped regions and a gate trench with rounded corners, achieved through a high-temperature step in a non-oxide and non-nitride forming atmosphere, followed by removal of the surface layer to ensure uniform gate dielectric thickness and reduced electric field peaks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a gate trench is formed in SiC substrate using conventional etching techniques, then the gate trench can be created, but the corners of the gate trench become uneven, leading to increased electric fields and higher susceptibility to failure
Solution Approach 1:
The patent applies a high-temperature thermal field (1000-1500°C) to reshape the gate trench corners from sharp/uneven to rounded. This parameter change in temperature transforms the SiC material at the trench corners, creating a rounded profile that reduces electric field concentration and improves device reliability.
Solution Approach 2:
The high-temperature treatment is performed as a preliminary step before forming the gate dielectric layer. By pre-rounding the trench corners before dielectric deposition, the patent ensures that the subsequent dielectric layer forms with uniform thickness, preventing future breakdown issues.
2Manufacturing precision
If thermal oxidation is applied at the SiC-gate dielectric interface, then the interface can be formed, but defects occur leading to lower electron mobility and increased on-resistance
Solution Approach 1:
The patent performs the high-temperature treatment in an inert atmosphere (nitrogen or argon) rather than an oxidizing atmosphere. This prevents thermal oxidation at the SiC-gate dielectric interface, avoiding the formation of defects that would reduce electron mobility and increase on-resistance.
Solution Approach 2:
The patent converts the potentially harmful high-temperature process (which could cause oxidation) into a beneficial treatment by controlling the atmosphere. The same high temperature that could cause damage is instead used to reshape the trench corners while the inert atmosphere prevents oxidation, turning a potential harm into a benefit.
3Power
If the gate dielectric is placed close to the SiC substrate to utilize SiC's high breakdown voltage, then voltage blocking capability is improved, but the gate dielectric becomes more susceptible to breakdown due to high electric fields
Solution Approach 1:
The patent performs high-temperature treatment in advance to round the trench corners before depositing the gate dielectric. This preliminary action creates a geometry that prevents electric field concentration, allowing the gate dielectric to be placed close to the SiC substrate without risking breakdown.
Solution Approach 2:
The patent changes the geometric parameters of the gate trench from sharp corners to rounded corners through high-temperature treatment. This parameter change in shape reduces electric field intensity at the dielectric-SiC interface, enabling the gate dielectric to withstand the high voltages that SiC can block.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes defects and enhances the breakdown characteristics of SiC transistors by providing a shielded gate structure with improved electron mobility and reduced susceptibility to leakage and dielectric breakdown, allowing for effective utilization of SiC's high voltage blocking capabilities.
Implementation Method 1
The substrate is annealed substrate so as to activate dopant atoms in the second, third and fourth doped regions
Implementation Method 2
A high-temperature step is applied to the substrate in a non-oxide and non-nitride forming atmosphere so as to realign silicon-carbide atoms along sidewalls of the gate trench and to form rounded corners between the bottom and sidewalls of the gate trench
Data Source
AI summary
A SIC transistor device includes a silicon-carbide semiconductor substrate having a plurality of first doped regions laterally spaced apart from one another and beneath a main surface of the substrate, a second doped region extending from the main surface to a third doped region that is above the first doped regions, and a plurality of fourth doped regions in the substrate extending from the main surface to the first doped regions. The second doped region has a first conductivity type. The first, third and fourth doped regions have a second conductivity type opposite the first conductivity type. A gate trench extends through the second and third doped regions. The gate trench has sidewalls, a bottom and rounded corners between the bottom and the sidewalls.