SiC Trench Contact Layout to Suppress A-Plane Defects

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Solution Overview

Problem

SiC semiconductor devices face challenges in suppressing a-plane defects, which degrade electrical characteristics and increase on-resistance due to crystal defects generated during contact region formation, particularly along a-plane surfaces.

Innovation Solution

The SiC semiconductor device incorporates contact regions of a p-type conductivity formed at intervals in the a-axis direction from the second outer side walls of the second trench structures, with a band-shaped configuration extending in the m-axis direction, and well regions to suppress a-plane defects and enhance breakdown voltage, while the trench structures and source regions are designed to penetrate through the body region and extend in specific directions to minimize defect formation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If contact regions are formed in conventional SiC semiconductor devices, then electrical connection is established, but a-plane defects are generated along a-plane surfaces which degrade electrical characteristics and increase on-resistance

Engineering Contradiction:
Improveelectrical characteristicsVSAvoida-plane defects
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent extracts and eliminates the harmful a-plane defects by carefully controlling the contact region formation process. Specifically, the contact regions are formed to avoid intersecting with a-plane crystal defects, and the epitaxial growth is controlled to prevent defect generation at contact interfaces, thereby removing the harmful factor while maintaining electrical connection functionality

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent applies local quality by creating different structural characteristics in different regions. The contact regions are specifically designed with optimized geometry and positioning to minimize defect formation in critical areas, while the epitaxial layer is grown with controlled orientation and quality in regions adjacent to contacts, ensuring high electrical characteristics where needed

Inventive Principle:
Principle #3Local quality

2Reliability

If contact region formation is expanded to improve electrical connection, then on-resistance decreases, but alignment deviations and defect formation increase

Engineering Contradiction:
Improveon-resistanceVSAvoidalignment precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent segments the contact region formation into multiple controlled steps and zones. Contact regions are divided into first and second contact regions with different functions and positions, allowing optimized formation processes for each segment. This segmentation enables better control of alignment and reduces the impact of deviations in any single region

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary actions by pre-defining the contact region patterns and positions before final formation. The contact regions are designed with predetermined geometries and spacing that account for potential alignment variations, and the epitaxial growth conditions are pre-optimized to ensure defect-free formation in the contact regions, thereby maintaining manufacturing precision even as contact area is expanded

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250022926A1Sic semiconductor device
Publication Date: 2025.01.16 ROHM CO LTD
  • US20250022926A1 patent drawing
  • US20250022926A1 patent drawing
  • US20250022926A1 patent drawing

AI summary

A semiconductor device (1A) includes a chip (2) that includes an SiC monocrystal and has a main surface (3), a trench structure (20) that has a first side wall (22A) extending in an a-axis direction of the SiC monocrystal and a second side wall (22B) extending in an m-axis direction of the SiC monocrystal and is formed in the main surface, and a contact region (50) of a first conductivity type that is formed in a region inside the chip along the trench structure at an interval in the a-axis direction from the second side wall.