SiC Trench Device Impurity Region Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Trench-type silicon carbide semiconductor devices face challenges in reducing potential drop and dielectric breakdown during high-speed switching due to high parasitic resistance in p-type wells, which is exacerbated by the use of silicon carbide with a wide bandgap, making it difficult to reduce electric resistance through doping.
Innovation Solution
Incorporating an impurity region in the non-element region of the silicon carbide semiconductor device as a path for displacement current, which reduces effective sheet resistance and potential drop, thereby minimizing dielectric breakdown by providing a low-resistance path for displacement currents through the second relaxation region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If silicon carbide is used as a semiconductor material to reduce losses and enable high-speed switching, then energy efficiency is improved, but parasitic resistance in p-type wells increases making it difficult to reduce electric resistance through doping
Solution Approach 1:
The patent introduces an impurity region with a first conductivity type (opposite to the p-type well) positioned between the drift layer and the p-type well in the outer peripheral region. This local modification creates a low-resistance path specifically where displacement current flows, without affecting the overall device structure or requiring extensive doping of the silicon carbide material itself.
Solution Approach 2:
The impurity region acts as an intermediary layer that mediates between the drift layer and the p-type well. It provides a low-resistance path for displacement current to flow from the drift layer to the p-type well, effectively reducing the parasitic resistance without requiring changes to the bulk silicon carbide material properties.
2Device complexity
If the p-type well cross-sectional area is increased in the outer peripheral region, then the well structure is simplified, but the displacement current path length increases causing high electric resistance and large potential drop
Solution Approach 1:
Instead of uniformly reducing the p-type well area throughout, the patent maintains the simplified well structure in the outer peripheral region but locally introduces an impurity region with opposite conductivity type. This creates a low-resistance path specifically in the displacement current flow path, reducing potential drop without complicating the overall well structure.
Solution Approach 2:
The patent addresses the two-dimensional trade-off between well area and path length by introducing a vertical dimension - the impurity region is positioned between the drift layer and p-type well in the vertical stacking direction, creating a low-resistance path that bypasses the horizontal distance issue.
3Loss of energy
If high-speed switching is implemented to further reduce losses, then energy efficiency is improved, but displacement current through parasitic capacitance increases causing larger potential drop and dielectric breakdown
Solution Approach 1:
The patent preemptively addresses the increased displacement current problem by introducing the impurity region before high-speed switching operations are implemented. This low-resistance path is prepared in advance to handle the larger displacement currents that will flow during high-speed switching, preventing dielectric breakdown before it occurs.
Solution Approach 2:
The impurity region provides a preliminary counter-measure against the harmful effect of increased displacement current. By creating an alternative low-resistance path before the problem manifests, it prevents the potential drop from reaching levels that would cause dielectric breakdown during high-speed switching operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces the magnitude of potential drop and dielectric breakdown between the second relaxation region and the gate potential, enhancing the reliability and performance of silicon carbide semiconductor devices during high-speed switching operations.
Implementation Method 1
the impurity region included in a path of the displacement current flowing through the second relaxation region reduces an effective sheet resistance
Implementation Method 2
a displacement current is generated through parasitic capacitance present between the p-type well and the n-type drift layer
Data Source
AI summary
A drift layer and a source region have a first conductivity type. A base region has a second conductivity type. A first trench penetrates the source region and the base region. A gate electrode is provided in the first trench through a gate insulation film. A first relaxation region is disposed below the first trench, and has the second conductivity type. A source pad electrode is electrically connected to the first relaxation region. A gate pad electrode is disposed in a non-element region. An impurity region is disposed in the non-element region, is provided on the drift layer, and has the first conductivity type. A second trench penetrates the impurity region. A second relaxation region is disposed below the second trench, and has the second conductivity type.