SiC Trench Schottky MOSFET Doping Layout for Low Leakage
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Solution Overview
Problem
Trench-gate silicon carbide semiconductor devices face challenges in balancing ON-state resistance and leakage current, with narrow trench gaps leading to insufficient unipolar current flow and increased electric fields that can cause reliability issues and breakdown of the gate insulating film.
Innovation Solution
A silicon carbide semiconductor device design featuring a Schottky barrier diode with a low-resistance layer of higher impurity concentration adjacent to the SBD trench and a lower impurity concentration adjacent to the gate trench, optimizing impurity concentrations to reduce leakage current and ON-state resistance while enhancing unipolar current flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the intervals between trench gates are kept narrow to moderate electric fields, then the concentration of electric fields at trench bottoms is reduced, but the current path becomes narrow and insufficient unipolar current flows through the SBD region
Solution Approach 1:
The patent applies local quality by creating a low-resistance layer with specific impurity concentration distribution localized in the SBD region between trench gates. This layer has higher impurity concentration near the Schottky electrode interface and lower concentration toward the gate electrode, providing locally optimized electrical properties that enhance unipolar current flow without affecting the overall trench gate structure or requiring wider intervals between trenches.
Solution Approach 2:
The patent changes the impurity concentration parameter within the low-resistance layer to optimize performance. By controlling the impurity concentration to be higher near the Schottky electrode and lower near the gate electrode, the patent achieves reduced ON-state resistance and enhanced unipolar current flow while maintaining reliable electric field distribution and gate insulating film integrity.
2Loss of energy
If the impurity concentration in the low-resistance layer is increased to reduce ON-state resistance, then the ON-state resistance decreases, but the electric field concentration at the gate insulating film increases causing breakdown
Solution Approach 1:
The patent applies local quality by creating a low-resistance layer with specific impurity concentration distribution localized in the SBD region between trench gates. This layer has higher impurity concentration near the Schottky electrode interface and lower concentration toward the gate electrode, providing locally optimized electrical properties that enhance unipolar current flow without affecting the overall trench gate structure or requiring wider intervals between trenches.
Solution Approach 2:
The patent changes the impurity concentration parameter within the low-resistance layer to optimize performance. By controlling the impurity concentration to be higher near the Schottky electrode and lower near the gate electrode, the patent achieves reduced ON-state resistance and enhanced unipolar current flow while maintaining reliable electric field distribution and gate insulating film integrity.
3Reliability
If the intervals between trenches are increased to reduce electric field concentration, then the electric field intensity at trench bottoms is reduced, but the Schottky current density decreases due to larger distances between protective layers
Solution Approach 1:
The patent applies local quality by creating a low-resistance layer with specific impurity concentration distribution localized in the SBD region between trench gates. This layer has higher impurity concentration near the Schottky electrode interface and lower concentration toward the gate electrode, providing locally optimized electrical properties that enhance unipolar current flow without affecting the overall trench gate structure or requiring wider intervals between trenches.
Solution Approach 2:
The patent changes the impurity concentration parameter within the low-resistance layer to optimize performance. By controlling the impurity concentration to be higher near the Schottky electrode and lower near the gate electrode, the patent achieves reduced ON-state resistance and enhanced unipolar current flow while maintaining reliable electric field distribution and gate insulating film integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively suppresses bipolar operation, reduces leakage current, and improves the density of unipolar current flow through built-in Schottky barrier diodes, enhancing the reliability and performance of the semiconductor device.
Implementation Method 1
a Schottky barrier diode electrode embedded in the second trench
Implementation Method 2
a gate electrode embedded in the first trench via a gate insulating film that covers an inner face of the first trench
Implementation Method 3
a first low-resistance layer of the first conductivity type provided in the semiconductor layer to have contact with at least one trench side wall of the first trench
Implementation Method 4
The second low-resistance layer has an impurity concentration higher than an impurity concentration in the semiconductor layer and lower than an impurity concentration in the first low-resistance layer
Data Source
AI summary
The present invention relates to a silicon carbide semiconductor device that includes a Schottky barrier diode in a field-effect transistor and includes a first trench provided through first and second semiconductor regions in a thickness direction and reaches inside a semiconductor layer, a second trench provided through the second semiconductor region in the thickness direction and reaches inside the semiconductor layer, a gate electrode embedded in the first trench via a gate insulating film, a Schottky barrier diode electrode embedded in the second trench, a first low-resistance layer having contact with a trench side wall of the first trench, and a second low-resistance layer having contact with a trench side wall of the second trench. The second low-resistance layer has an impurity concentration that is higher than the impurity concentration in the semiconductor layer and lower than the impurity concentration in the first low-resistance layer.