SiC Trench Gate Alignment via Recess Ion Implantation
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Solution Overview
Problem
Conventional methods for manufacturing silicon carbide (SiC) semiconductor devices with trench gate structures face challenges in achieving accurate alignment of electric field relaxation layers, leading to increased on-resistance and reduced depth of the electric field relaxation layer due to the need for high acceleration energy in ion implantation, which also generates crystal defects and increases manufacturing costs.
Innovation Solution
A method involving the formation of recesses on the substrate surface, followed by ion implantation of impurities at the bottom of these recesses to create electric field relaxation layers without requiring large acceleration energy, allowing for accurate alignment and reducing the need for multiple implantation steps, thereby minimizing crystal defects and manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If ion implantation is performed with large acceleration energy to form electric field relaxation layer with large depth, then the depth of electric field relaxation layer is improved, but crystal defects are generated and manufacturing cost increases
Solution Approach 1:
The patent divides the ion implantation process into multiple steps with different acceleration energies. First, ions are implanted with large acceleration energy to reach deep regions, then additional ions are implanted with low acceleration energy to fill intermediate regions. This segmentation allows formation of a deep electric field relaxation layer without generating excessive crystal defects from single high-energy implantation.
Solution Approach 2:
The patent performs preliminary ion implantation with large acceleration energy to create the deep portion of the electric field relaxation layer before performing subsequent implantation with low acceleration energy. This preliminary action establishes the deep foundation first, then the second implantation fills in the intermediate regions without causing excessive damage.
2Length of stationary object
If multiple ion implantation steps are performed to form electric field relaxation layer with large depth, then the depth of electric field relaxation layer is improved, but the number of manufacturing steps increases
Solution Approach 1:
The patent combines multiple ion implantation steps into a single integrated process flow. The first implantation with large acceleration energy and the second implantation with low acceleration energy are performed sequentially as part of one manufacturing cycle, sharing the same process equipment and control system, thereby reducing overall manufacturing complexity despite multiple implantation actions.
3Reliability
If electric field relaxation layer is disposed closer to trench gate to relax electric field, then electric field relaxation effect is improved, but alignment accuracy becomes more critical and on-resistance increases
Solution Approach 1:
The patent creates electric field relaxation layers with different depths at different locations. By forming the relaxation layer bottom at varying depths relative to the trench gate, the patent optimizes the balance between electric field relaxation effect and alignment tolerance. Regions requiring stronger relaxation have deeper layers, while regions prioritizing low on-resistance have shallower layers, allowing local optimization of the trade-off.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of SiC semiconductor devices with improved electric field relaxation and reduced on-resistance, while maintaining alignment accuracy between the electric field relaxation layers and the trench gate, thus extending the life of the gate oxide film and enhancing the device's performance.
Implementation Method 1
forming a plurality of electric field relaxation layers having the second conductivity type to be separated from each other on the cross section by ion-implanting a second conductivity type impurity
Data Source
AI summary
A method for manufacturing a SiC semiconductor device includes: forming recesses to be separated from each other on a cross section in parallel to a surface of the substrate by partially removing a top portion of the drift layer with etching using a mask after arranging the mask on a front surface of a drift layer; forming electric field relaxation layers having the second conductivity type to be separated from each other on the cross section by ion-implanting a second conductivity type impurity on a bottom of each recess using the mask; and forming a channel layer by forming a second conductivity type layer on the front surface of the drift layer including a front surface of each electric field relaxation layer in a respective recess.