SiC Trench Gate Structure with Lateral Electric Field Block Layer
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Solution Overview
Problem
In SiC semiconductor devices with trench gate structures, the density of trench gates is limited by the need to accommodate an electric field relaxation layer, making it difficult to narrow the distance between trench gates and thereby reducing channel resistance effectively.
Innovation Solution
The semiconductor device incorporates a configuration with a stripe-patterned electric field block layer and JFET portion, allowing for a narrower connection layer and increased trench gate density by aligning the trench gate structure with the JFET and electric field block layer directions, enabling a higher channel density and reduced channel resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an electric field relaxation layer is formed below the base layer between opposing trench gates, then dielectric breakdown is prevented, but the distance between trench gates cannot be narrowed and channel resistance cannot be reduced effectively
Solution Approach 1:
The patent transitions from a vertical arrangement (relaxation layer between trenches) to a lateral arrangement (block layers extending from trench sides). The electric field block layers are positioned laterally adjacent to the trench gates rather than vertically between them, changing the spatial dimension of electric field management and enabling tighter trench spacing.
Solution Approach 2:
The patent applies electric field blocking functionality locally at critical regions where high electric fields concentrate (at the trench gate sides), rather than requiring a continuous relaxation layer throughout the entire inter-trench region. This localized approach allows selective positioning of block layers only where needed for field control.
2Productivity
If trench gate density is increased to reduce channel resistance, then on-state resistance decreases, but dielectric breakdown risk increases due to higher electric field concentration
Solution Approach 1:
The patent preemptively counteracts the harmful electric field concentration that would result from increased trench density by positioning electric field block layers adjacent to the trench gates. These blocks prevent the formation of excessive electric fields before they can cause dielectric breakdown, enabling higher trench density without compromising reliability.
Solution Approach 2:
The electric field block layers act as intermediary structures between adjacent trench gates, mediating the electric field distribution in the high-stress regions. These blocks serve as buffer elements that protect the dielectric material from breakdown while allowing the trench gates to be positioned closer together.
3Productivity
If the distance between trench gates is narrowed, then channel density increases and on-state resistance decreases, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary electric field management by positioning block layers during the formation process, before final trench gate patterning and alignment. This preliminary structuring of the electric field environment allows subsequent processing steps to focus on trench gate fabrication without the added complexity of simultaneously managing inter-trench field distribution.
Data Source
AI summary
A semiconductor device includes an inversion type semiconductor element, which has: a substrate; a drift layer; a saturation current suppression layer; a current dispersion layer; a base region; a source region; a connection layer; a plurality of trench gate structures; an interlayer insulation film; a source electrode; and a drain electrode. A channel region is provided in a portion of the base region in contact with each trench gate structure by applying a gate voltage to the gate electrode and applying a normal operation voltage as a drain voltage to the drain electrode; and a current flows between the source electrode and the drain electrode through the source region and the JFET portion.