SiC Trench Gate Structure for Higher Breakdown Voltage
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Solution Overview
Problem
Silicon carbide trench power devices face a high risk of gate breakdown due to large electric fields applied to the gate dielectric layer, affecting the voltage withstand level.
Innovation Solution
A manufacturing method involving the simultaneous formation of gate and source trenches, with a thick first insulating layer protecting the gate and a p-type doped region under the source trench to limit the electric field, enhancing the voltage withstand level by ensuring the gate is not easily broken down.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a thin epitaxial layer is used in silicon carbide device to reduce on-resistance, then the voltage withstand level is maintained, but the gate is easily broken down due to large electric field
Solution Approach 1:
The gate structure is segmented into two gates (first gate and second gate) separated by a first insulating layer. This segmentation distributes the electric field across multiple interfaces, preventing concentration at a single gate dielectric interface and reducing breakdown risk while maintaining voltage withstand capability
Solution Approach 2:
A first insulating layer is introduced as an intermediary between the first gate and second gate. This insulating layer acts as a buffer that distributes the electric field and protects both gates from direct exposure to high electric field stress, thereby improving gate reliability
2Reliability
If a thick insulating layer is formed in the gate trench to protect the gate, then the gate breakdown risk is reduced, but the device complexity increases
Solution Approach 1:
The formation of the first insulating layer is merged with the existing gate dielectric layer formation process. The first insulating layer is formed simultaneously with or integrated into the gate dielectric layer deposition, combining multiple functions into a single process step and reducing overall device complexity
Solution Approach 2:
The first insulating layer serves multiple functions: it acts as a protective layer for the first gate, a field distribution medium, and an interface between the two gates. This multi-functionality reduces the need for additional separate layers and processes, simplifying the overall device structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method reduces the risk of gate breakdown and improves the voltage withstand level of the semiconductor device by distributing the electric field effectively, allowing for a lower on-resistance while maintaining the same voltage level as traditional silicon devices.
Implementation Method 1
a large electric field is applied to a gate dielectric layer in a gate trench when the trench power device is in operation so that the gate is easily broken down
Implementation Method 2
P-type ion implantation is performed so that a p-type doped region under the source trench is formed in the second n-type semiconductor layer
Data Source
AI summary
A gate trench and a source trench are formed simultaneously in the same etching process, a p-type semiconductor layer and a p-type doped region can be contacted in a self-aligned manner in the source trench, and the process is simple. A first insulating layer and a first gate are formed in a lower part of the gate trench, and a second insulating layer and a second gate are formed in an upper part of the gate trench so that the thick first insulating layer can protect the second gate from being easily broken down, the first gate can increase an electric field near a bottom of the gate trench, and thus a voltage withstand level of the semiconductor device can be improved. A bottom of the source trench can penetrate deep into a second n-type semiconductor layer.