SiC Trench Gate Deep Layer Reduces Electric Field Concentration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Silicon carbide (SiC) semiconductor devices face challenges in reducing electric field concentration in gate insulating layers, leading to potential damage and production yield issues due to the high breakdown field strength, especially when trench gate structures are applied, and misalignment during manufacturing processes affects device properties.
Innovation Solution
The SiC semiconductor device incorporates a deep layer formed perpendicular to the trench, reducing electric field concentration and improving yield by allowing for independent mask alignment during manufacturing, and includes a P+ type body layer to enhance breakdown voltage and reduce on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a trench gate structure is applied to increase current control capability, then the device can control high current, but the gate insulating layer receives excessive electric field concentration causing damage
Solution Approach 1:
The patent applies local quality by creating a deep layer with different conductivity type and impurity concentration specifically at the bottom portion of the trench gate structure. This localized modification reduces electric field concentration at the critical bottom region where the gate insulating layer is most vulnerable, while maintaining the overall trench gate structure's current control capability.
Solution Approach 2:
The patent changes physical parameters by introducing a deep layer with different conductivity type (opposite to the drift layer) and different impurity concentration. This parameter change modifies the electric field distribution profile, reducing peak electric field concentration at the trench bottom and protecting the gate insulating layer from damage.
2Device complexity
If the deep layer is formed parallel to the trench gate direction, then the structure is simple, but mask misalignment during manufacturing affects device properties
Solution Approach 1:
The patent applies preliminary anti-action by deliberately designing the deep layer to extend beyond the trench gate structure in a perpendicular direction. This over-extension creates a built-in alignment tolerance that compensates for potential mask misalignment during manufacturing, preventing harmful effects before they can occur.
Solution Approach 2:
The patent transitions from a one-dimensional parallel arrangement (deep layer parallel to trench gate) to a two-dimensional L-shaped configuration (deep layer perpendicular to trench gate). This dimensional change decouples the mask alignment requirements, allowing independent positioning and improving manufacturing precision.
3Object-affected harmful factors
If the gate insulating layer thickness is increased to reduce electric field concentration, then electric field relaxation is achieved, but the device size and complexity increase
Solution Approach 1:
Instead of uniformly increasing the gate insulating layer thickness throughout the trench, the patent applies local quality by introducing a deep layer with modified electrical properties specifically at the bottom portion. This localized approach reduces electric field concentration where it is most critical without increasing the overall device size or requiring thicker insulation everywhere.
Solution Approach 2:
The patent changes the electrical parameters (conductivity type and impurity concentration) of the deep layer to achieve electric field relaxation, rather than changing the physical dimension (thickness) of the gate insulating layer. This parameter change approach reduces electric field concentration while maintaining compact device dimensions.
Data Source
AI summary
A silicon carbide semiconductor device includes a substrate, a drift layer located on a first surface of the substrate, a base region located on the drift layer, a source region located on the base region, a trench penetrating the source region and the base region to the drift layer, a channel layer located in the trench, a gate insulating layer located on the channel layer, a gate electrode located on the gate insulating layer, a source electrode electrically coupled with the source region and the base region, a drain electrode located on a second surface of the substrate, and a deep layer. The deep layer is located under the base region, extends to a depth deeper than the trench and is formed along an approximately normal direction to a sidewall of the trench.