SiC Trench Gate Structure for Higher Channel Density

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Solution Overview

Problem

Power semiconductor devices using silicon carbide face limitations in reducing channel density due to electric field concentration and structural constraints in trench-type gate structures, which affect high-speed switching and heat management.

Innovation Solution

A silicon carbide-based power semiconductor device with a trench gate structure design that includes a recessed trench, a gate insulating layer, and a gate electrode layer, along with a well region, source region, and channel region, which alleviates electric field concentration and increases channel density through optimized doping and layer formation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If a trench type of gate structure is used to increase channel density, then channel density increases, but electric field concentration occurs at the trench edge

Engineering Contradiction:
Improvechannel densityVSAvoidelectric field concentration
Core Design Contradiction:
Quantity of substanceVSObject-affected harmful factors

Solution Approach 1:

A gate insulating layer is introduced as an intermediary between the gate electrode and the semiconductor layer. This insulating layer is disposed on the inner wall of the trench and prevents direct contact, thereby eliminating electric field concentration at the trench edge while preserving the high channel density advantage of the trench gate structure

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent changes the electrical parameters at the trench edge by introducing the gate insulating layer with specific dielectric properties. This modifies the electric field distribution pattern, preventing concentration at the trench edge while maintaining the overall high channel density structure

Inventive Principle:
Principle #35Parameter changes

2Quantity of substance

If source contact structure is disposed between gate electrodes, then device functionality is achieved, but distance between gate electrodes cannot be decreased

Engineering Contradiction:
Improvechannel densityVSAvoiddistance between gate electrodes
Core Design Contradiction:
Quantity of substanceVSLength of moving object

Solution Approach 1:

The patent transitions from a planar arrangement where source contacts are positioned between gate electrodes to a vertical arrangement where source contacts are formed on the bottom surface of the trench. This dimensional change allows gate electrodes to be positioned closer together horizontally while maintaining proper source contact functionality through the vertical contact path

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If silicon carbide is used instead of silicon, then high temperature stability and breakdown voltage are improved, but manufacturing complexity increases

Engineering Contradiction:
Improvehigh temperature stabilityVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent segments the gate structure into distinct functional layers: gate electrode layer, gate insulating layer, and the underlying semiconductor layer with drift region and well region. This segmentation allows each layer to be optimized for silicon carbide processing while maintaining overall device functionality, thereby managing manufacturing complexity through modular structure design

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS12191386B2Power semiconductor device and method of fabricating the same
Publication Date: 2025.01.07 HYUNDAI MOBIS CO LTD
  • US12191386B2 patent drawing
  • US12191386B2 patent drawing
  • US12191386B2 patent drawing

AI summary

A power semiconductor device includes a semiconductor layer of silicon carbide (SiC), at least one trench that extends in one direction, a gate insulating layer disposed on at least an inner wall of the at least one trench, at least one gate electrode layer disposed on the gate insulating layer, a drift region disposed in the semiconductor layer at least on one side of the at least one gate electrode layer, a well region disposed in the semiconductor layer to be deeper than the at least one gate electrode layer, a source region disposed in the well region, and at least one channel region disposed in the semiconductor layer of one side of the at least one gate electrode layer between the drift region and the source region.