SiC Trench Gate Semiconductor Device Reducing On-Resistance
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Solution Overview
Problem
Current semiconductor devices face challenges in reducing on-resistance, which affects their performance and efficiency.
Innovation Solution
The semiconductor device incorporates a specific structure with multiple electrode regions and semiconductor regions of different conductivity types, including silicon carbide, arranged in a manner that increases the surface area of the channel and relaxes the electric field, utilizing trench gate electrodes and insulating films to reduce on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional semiconductor device structures are used, then manufacturing simplicity is maintained, but on-resistance cannot be sufficiently reduced
Solution Approach 1:
The device is divided into multiple distinct regions including first and second electrode regions, first through fourth semiconductor regions with different conductivity types, and multiple insulating films. This segmentation allows each region to be optimized for specific functions, enabling reduced on-resistance through carefully controlled electric field distribution and carrier transport paths
Solution Approach 2:
Different regions are assigned different conductivity types (n-type and p-type) and doping concentrations to create locally optimized electrical properties. The first semiconductor region has first conductivity type while the second has second conductivity type, with specific doping concentrations that vary by region to control carrier concentration and electric field distribution, thereby reducing on-resistance in critical areas
Data Source
AI summary
According to one embodiment, a semiconductor device includes a first electrode, a second electrode, first to fourth semiconductor regions and a first insulating film. The second electrode includes first, second, and third electrode regions. The first semiconductor region includes first, second, third, fourth, and fifth partial regions. The first partial region is separated from the first electrode. The second partial region is separated from the first electrode region. The fourth partial region is separated from the second electrode region. The second semiconductor region includes sixth, seventh, eighth and ninth partial regions. The third semiconductor region is connected to the second semiconductor region. The fourth semiconductor region is electrically connected to the second electrode. The fourth semiconductor region includes tenth, eleventh, and twelfth partial regions. The first insulating film is provided between the first, third, and fourth semiconductor regions.