SiC Trench Gate Device with Floating Protective Layer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In trench gate type silicon carbide semiconductor devices, the breakdown voltage is limited by the electric field strength of the gate insulating film, leading to dielectric breakdown and increased on-resistance due to electric field concentration at trench corners, and existing solutions like protective diffusion layers either fail to adequately suppress JFET resistance or compromise the gate insulating film's protective effect.
Innovation Solution
A semiconductor device design featuring a floating protective diffusion layer during the ON state and grounding during the OFF state, with a specific structure including a first semiconductor layer, a gate trench, a gate insulating film, and additional semiconductor layers to manage depletion layers and electric field distribution, thereby suppressing JFET resistance and protecting the gate insulating film.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a protective diffusion layer is provided under the trench to protect the gate insulating film, then the breakdown voltage is improved, but the JFET resistance increases due to depletion layer formation between adjacent trenches
Solution Approach 1:
The protective diffusion layer is configured to change its electrical state dynamically: it forms a depletion layer during OFF state to protect the gate insulating film, and becomes conductive during ON state to reduce JFET resistance. This dynamic behavior resolves the contradiction between breakdown voltage protection and on-resistance reduction.
Solution Approach 2:
The electrical parameters (conductivity, potential) of the protective diffusion layer are changed based on operating conditions. By adjusting the impurity concentration and depth of the protective diffusion layer, the depletion layer width is controlled to balance between electric field protection and resistance reduction, resolving the technical contradiction.
2Productivity
If the trench spacing is narrowed to increase device density, then the productivity is improved, but the JFET resistance increases due to depletion layer overlap
Solution Approach 1:
The protective diffusion layer dynamically adjusts its conductivity based on operating state. During ON state, it becomes conductive to minimize JFET resistance even when trench spacing is narrow, enabling high device density without sacrificing on-resistance performance.
Solution Approach 2:
The protective diffusion layer has different impurity concentrations at different depths and positions. The local quality is optimized so that regions closer to the trench have higher impurity concentration to reduce depletion width and JFET resistance, while maintaining overall breakdown voltage protection.
3Reliability
If a p-type diffusion layer is disposed in the upper portion to suppress JFET resistance during ON state, then the on-resistance is reduced, but the protective effect of the gate insulating film is lowered during OFF state
Solution Approach 1:
The protective diffusion layer has non-uniform impurity concentration distribution with higher concentration near the trench and lower concentration deeper in the drift layer. This local quality variation allows it to suppress JFET resistance during ON state while maintaining adequate protective effect during OFF state.
Solution Approach 2:
The impurity concentration parameter of the protective diffusion layer is optimized to achieve dual functionality: sufficient concentration to reduce JFET resistance during ON state, but controlled concentration gradient to maintain depletion layer protection during OFF state.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively suppresses JFET resistance during the ON state and protects the gate insulating film during the OFF state, improving the breakdown voltage and switching characteristics by optimizing the potential and depletion layer distribution.
Implementation Method 1
a depletion layer is formed in the drift layer between the protective diffusion layers provided between adjacent trenches
Data Source
AI summary
A first semiconductor layer of a first conductivity type, a first semiconductor region of a second conductivity type provided in an upper layer part thereof, a second semiconductor region of the first conductivity type provided in the upper layer part thereof, a gate trench penetrating through the first and second semiconductor regions in a thickness direction and a bottom surface thereof reaching inside of the first semiconductor layer, a gate insulating film in the gate trench, a gate electrode embedded in the gate trench, a second semiconductor layer of the second conductivity type provided so as to extend, from the bottom surface of the gate trench, a third semiconductor layer of the second conductivity type extending to a position deeper than the bottom surface of the gate trench, and a fourth semiconductor layer of the first conductivity type interposed between the second semiconductor layer and the third semiconductor layer in the position deeper than the bottom surface of the gate trench.