SiC Trench MOSFET Structure for Tight Cell Pitch and Gate Insulation

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Solution Overview

Problem

Conventional vertical MOSFETs with trench structures face challenges in reducing cell pitch due to issues with electric field concentration on the gate insulating film, leading to reliability concerns and increased ON resistance, especially when using wide bandgap semiconductor materials like silicon carbide.

Innovation Solution

The semiconductor device incorporates a structure with a first and second p+-type region, where the first p+-type region is doped with a higher impurity concentration than the p-type base layer and extends deeper towards the drain electrode, and a second p+-type region is provided in a striped shape parallel to the trench, along with a thick interlayer insulating film and a barrier metal, to mitigate electric field concentration and ensure insulation between the gate and source electrodes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a trench structure is formed in a vertical MOSFET to increase cell density, then current density per unit area is increased, but electric field concentrates at the bottom of the trench causing reliability degradation

Engineering Contradiction:
Improvecell density per unit areaVSAvoidgate insulating film reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies local quality by providing a p+-type base region specifically at the bottom of the trench where electric field concentration occurs, rather than uniformly modifying the entire structure. This localized doping creates a pn junction that selectively mitigates the electric field concentration problem at the critical bottom region while maintaining the overall trench structure's high cell density advantage

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The p+-type base region acts as an intermediary element between the n-type drift layer and the gate insulating film. By introducing this intermediate layer with different semiconductor type and higher impurity concentration, the patent creates a pn junction that serves as a buffer to reduce electric field concentration, thereby protecting the gate insulating film from direct exposure to high electric fields

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If a p+-type base region is provided at the bottom of the trench to mitigate electric field concentration, then reliability is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvegate insulating film reliabilityVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the p+-type base region formation with the existing trench fabrication process by using the same ion implantation steps. The p+-type region is created by implanting dopants through the trench opening during the base layer formation process, combining multiple functions (trench formation, base region creation, and electric field management) into a unified manufacturing approach rather than requiring separate complex processing steps

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration allows for a reduced cell pitch without increasing ON resistance, improving reliability and facilitating plating and nickel silicide coverage, eliminating the need for tungsten plugs, even at pitches below 4.0 μm.

Implementation Method 1

a first p+-type region (3) selectively formed in the n-type region (15) so as to entirely cover a bottom of a trench (1030)... an impurity concentration of the first p+-type region being higher than an impurity concentration of the p-type base layer

Methodology Applied
Scientific EffectImpurity doping: Dopants

Implementation Method 2

a gate insulating film provided on the trench; an interlayer insulating film provided on the gate electrode in the trench

Methodology Applied
Scientific EffectElectrical insulation: Dielectric

Data Source

PatentUS12094939B2Semiconductor device having a gate electrode, an interlayer insulating film and a barrier metal provided in a trench
Publication Date: 2024.09.17 FUJI ELECTRIC CO LTD
  • US12094939B2 patent drawing
  • US12094939B2 patent drawing
  • US12094939B2 patent drawing

AI summary

At a front surface of a silicon carbide base, an n−-type drift layer, a p-type base layer, a first n+-type source region, a second n+-type source region, and a trench that penetrates the first and the second n+-type source regions and the p-type base layer and reaches the n-type region are provided. In the trench, the gate electrode is provided via a gate insulating film, an interlayer insulating film is provided in the trench on the gate electrode, and a barrier metal is provided in the trench on the interlayer insulating film.