SiC Trench Gate Layout for Gate Dielectric Field Relaxation
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Solution Overview
Problem
Semiconductor devices using SiC substrates face reliability issues due to electric field concentration in the gate dielectric film, leading to potential breakdown and reduced reliability compared to Si substrate devices.
Innovation Solution
The semiconductor device incorporates a trench gate type power transistor with a p-type first semiconductor region and a p-type second semiconductor region of varying widths, where the p-type second semiconductor region in the peripheral region is narrower than in the cell region, to relax electric field concentration and enhance reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SiC substrate is used to improve the trade-off relationship between on-resistance and withstand voltage, then the on-resistance decreases and withstand voltage increases, but electric field concentration occurs in the gate dielectric film leading to breakdown and reduced reliability
Solution Approach 1:
The patent introduces a relaxation region with different material composition or structure at the interface between the semiconductor substrate and the first epitaxial film. This local modification creates a gradient in electrical properties that specifically addresses the electric field concentration problem at the critical interface region, while maintaining the high withstand voltage characteristics of SiC in the bulk material.
Solution Approach 2:
The relaxation region acts as an intermediary layer between the semiconductor substrate and the first epitaxial film. It mediates the electric field distribution by providing a transition zone that gradually changes the dielectric constant or carrier concentration, thereby reducing the abrupt field concentration that would otherwise occur at the sharp interface.
2Object-affected harmful factors
If electric field relaxation area is provided to reduce electric field concentration, then electric field distribution is improved, but sufficient reliability may not be obtained depending on the configuration
Solution Approach 1:
The relaxation region is segmented into multiple sub-regions with different properties along the depth direction. The first relaxation region is positioned at the interface between the semiconductor substrate and the first epitaxial film, while the second relaxation region is at the interface between the first and second epitaxial films. This segmentation allows each region to address specific local electric field concentration issues.
Solution Approach 2:
The patent modifies physical parameters such as impurity concentration, layer thickness, or material composition within the relaxation regions to optimize electric field distribution. By carefully controlling these parameters, the relaxation regions achieve effective field smoothing without compromising the overall device reliability or performance.
Data Source
AI summary
Semiconductor device has a cell region and a peripheral region, and has a drift layer, a trench, an gate dielectric film on an inner wall of the trench, a gate electrode, and a p-type first semiconductor region below the trench in the cell region on a semiconductor substrate. Further, in the peripheral region on the semiconductor substrate, p-type second semiconductor region is formed in the same layer as the p-type first semiconductor region, a width of the p-type first semiconductor region and a width of the p-type second semiconductor region are different.