SiC Trench Gate Structure for Leakage Reduction
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Solution Overview
Problem
Silicon carbide (SiC) MOSFETs face challenges in reducing off-leak current and on-resistance, particularly due to the high field strength and crystal defects at the gate trench bottom region, which increase power consumption and reliability issues.
Innovation Solution
The implementation of a trench gate structure with a double trench design, including a p+-type field relaxation region and an n-type high concentration region, separates the gate trench bottom region from the high concentration region, reducing the field strength and off-leak current, and enhancing the channel area per unit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the gate trench bottom region has high field strength, then the trench gate structure achieves low on-resistance, but reliability decreases due to increased off-leak current and crystal defects
Solution Approach 1:
The patent introduces a p-type field relaxation region with higher impurity concentration localized at the gate trench bottom region. This local quality modification specifically addresses the reliability issue by reducing the electric field strength and crystal defects at the critical trench bottom area, while maintaining the overall trench gate structure that provides low on-resistance.
Solution Approach 2:
The patent converts the harmful high field strength and crystal defects at the gate trench bottom into a beneficial configuration by introducing a p-type field relaxation region. This region, with its higher impurity concentration, actually improves reliability by reducing off-leak current and mitigating the harmful effects of the high field strength, while the trench gate structure continues to provide low on-resistance.
2Ease of manufacture
If a simple trench gate structure is used, then manufacturing is easier, but off-leak current increases due to lack of field relaxation regions
Solution Approach 1:
The patent enhances the simple trench gate structure by adding a p-type field relaxation region with higher impurity concentration at the gate trench bottom. This localized modification effectively reduces off-leak current by managing the electric field distribution, while the overall manufacturing process remains relatively straightforward and compatible with existing semiconductor fabrication techniques.
Data Source
AI summary
A semiconductor device according to an embodiment includes: a SiC layer having a first plane and a second plane facing the first plane, the SiC layer including a first trench on a first plane side, an n-type first SiC region, a p-type second SiC region, an n-type third SiC region located in this order from the second plane to the first plane, a p-type fourth SiC region between the first SiC region and the first trench, a fifth SiC region between the first SiC region and the first plane, and a sixth SiC region between the fourth SiC region and the fifth SiC region, and the sixth SiC region having an n-type impurity concentration higher than an n-type impurity concentration of the first SiC region; a gate electrode in the first trench; a first electrode on the first plane side; and a second electrode on a second plane side.