SiC Trench Gate Leakage Reduction via Localized Doping
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Solution Overview
Problem
Existing semiconductor devices, particularly MOSFETs, face challenges in reducing leakage current between the source and drain during off-operation, leading to increased power consumption due to concentrated electric fields and crystal defects at high p-type impurity concentrations.
Innovation Solution
The semiconductor device employs a silicon carbide-based trench gate structure with a double trench design, including a high concentration region of p++ type between contact trenches and an electric field relaxation region with varying p-type impurity concentrations to reduce leakage current and power consumption, while maintaining low on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If high p-type impurity concentration is applied to reduce leakage current, then leakage current between source and drain is reduced, but crystal defects increase and power consumption increases
Solution Approach 1:
The patent applies different p-type impurity concentrations in different regions: high concentration in the electric field relaxation region to reduce leakage current, and low concentration in the high concentration region to minimize crystal defects. This spatial differentiation of impurity concentration resolves the contradiction between reducing leakage current and minimizing power consumption.
Solution Approach 2:
The patent segments the semiconductor structure into distinct regions with different impurity concentrations: the electric field relaxation region with high p-type concentration and the high concentration region with low p-type concentration. This segmentation allows each region to perform its specific function optimally, reducing overall power consumption while maintaining low leakage current.
2Object-generated harmful factors
If high p-type impurity concentration is applied at the trench bottom, then leakage current is reduced, but crystal defects increase
Solution Approach 1:
The patent implements local quality by positioning high p-type impurity concentration specifically in the electric field relaxation region away from the trench bottom, while maintaining low p-type impurity concentration in the high concentration region near the trench bottom. This localized differentiation reduces crystal defects while still effectively reducing leakage current through the electric field relaxation region.
3Power
If trench gate structure is applied to reduce on-resistance, then channel area per unit area increases, but leakage current increases
Solution Approach 1:
The patent changes the electrical parameters by introducing p-type impurity regions with different concentrations around the trench gate structure. The electric field relaxation region with high p-type concentration modifies the electric field distribution to reduce leakage current, while the low on-resistance is maintained through the trench gate's increased channel area.
Data Source
AI summary
A semiconductor device of an embodiment includes: a first trench located in a silicon carbide layer extending in a first direction; a second trench and a third trench adjacent to each other in the first direction; n type first silicon carbide region; p type second silicon carbide region on the first silicon carbide region; n type third silicon carbide region on the second silicon carbide region; p type fourth silicon carbide region between the first silicon carbide region and the second trench; p type fifth silicon carbide region between the first silicon carbide region and the third trench; p type sixth silicon carbide region shallower than the second trench between the second trench and the third trench and having a p type impurity concentration higher than that of the second silicon carbide region; a gate electrode in the first trench; a first electrode, and a second electrode.