SiC Trench Gate MOSFET with Arc-Shaped Sidewalls
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Solution Overview
Problem
Conventional silicon carbide trench-gate MOSFETs face challenges with dielectric breakdown of the gate insulating film due to high electric fields concentrating on the bottom surface of the gate trench, leading to potential erosion of source regions and reduced reliability.
Innovation Solution
A semiconductor device with a trench structure having a uniform gate insulating film thickness and impurity concentration profiles that inhibit local electric field concentration, featuring a third semiconductor region with a gradually decreasing or constant impurity concentration depth profile and arc-shaped sidewalls, along with a method involving epitaxial layer growth, ion implantation, and hydrogen silane treatment for trench formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate insulating film thickness is increased at the bottom surface of the gate trench to prevent dielectric breakdown, then the reliability of the gate insulating film is improved, but the cell area increases and manufacturing complexity increases
Solution Approach 1:
The patent applies local quality by creating a gate trench with non-uniform width where the third portion (bottom portion) has a larger width than the first and second portions. This local variation in geometry distributes the electric field more evenly along the gate insulating film, preventing concentration at the bottom surface while maintaining uniform film thickness throughout, thus improving reliability without increasing complexity
Solution Approach 2:
The patent employs curvature by forming arc-shaped sidewalls in the gate trench instead of straight vertical walls. The curved geometry, particularly in the third portion with larger width, helps to smooth out electric field distribution and eliminate sharp corners where field concentration would occur, thereby enhancing gate insulating film reliability while maintaining a relatively simple trench structure
2Productivity
If conventional trench gate structure is used to increase cell density, then the cell width is reduced and cell density per unit area is increased, but the electric field concentrates on the bottom surface of the gate trench causing dielectric breakdown
Solution Approach 1:
The patent resolves this contradiction by making the gate trench width vary locally along its depth. The third portion at the bottom has a larger width compared to the upper portions, which creates a more uniform electric field distribution along the entire gate insulating film surface. This prevents field concentration at the bottom while maintaining the compact trench structure needed for high cell density
Solution Approach 2:
The curved sidewalls, particularly the arc-shaped configuration in the third portion, eliminate sharp geometric features that would cause electric field concentration. This curvature approach allows the trench to maintain a compact footprint for high cell density while distributing the electric field uniformly to prevent dielectric breakdown
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively increases the dielectric breakdown field strength and improves the reliability of the gate insulating film, reducing leakage currents and enhancing long-term performance.
Implementation Method 1
an n+ source region is selectively formed in the p-type silicon carbide epitaxial layer using ion implantation
Implementation Method 2
the oxidation speed of the (000-1) plane (the so-called c-plane) of silicon carbide is approximately five times greater than the oxidation speed of crystal planes orthogonal to the c-plane, the bottom surface of the gate trench is set to be a c-plane, and the gate insulating film is formed using thermal oxidation
Data Source
AI summary
A gate trench of a MOS gate formed in the front surface of a silicon carbide substrate includes a first portion that includes the bottom surface of the gate trench, a second portion that is connected to the substrate front surface side of the first portion, and a third portion that is connected to the substrate front surface side of the second portion. In the third portion of the gate trench, an n+ source region is exposed along the sidewalls. The width of the third portion of the gate trench is greater than the widths of the first and second portions and of the gate trench. Upper corners of the gate trench smoothly connect the sidewalls to the substrate front surface. The thickness of a gate insulating film smoothly connected along the bottom surface and sidewalls of the gate trench is substantially uniform over the entire inner wall surface of the gate trench.