SiC Trench Gate MOSFET Deep and Guard Ring Trench Width Matching
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Solution Overview
Problem
In silicon carbide (SiC) semiconductor devices, the high breakdown field strength leads to excessive electric field concentration at the bottom of trench gate MOSFETs, causing gate insulating film breakdown, and the embedded epitaxial technique for forming p-type deep and guard ring layers results in shape abnormalities and surface irregularities, which hinder the relaxation of the electric field and lead to leakage through the gate insulating film.
Innovation Solution
The semiconductor device and manufacturing method involve forming deep trenches and guard ring trenches of the same width, allowing for epitaxial growth of a p-type impurity layer that fills these trenches uniformly, thereby preventing shape abnormalities and irregularities, and ensuring a planar surface for subsequent processing, which reduces leakage through the gate insulating film.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the embedded epitaxial technique is used to form a p-type deep layer and p-type guard ring layer, then the electric field at the bottom of the trench can be relaxed, but shape abnormalities and surface irregularities occur
Solution Approach 1:
The patent divides the trench structure into two distinct types: deep trenches for the p-type deep layer and guard ring trenches for the p-type guard ring layer. This segmentation allows each trench type to be optimized independently for its specific function, preventing the shape abnormalities that occur when both layers are formed in the same trench structure.
Solution Approach 2:
The patent applies different structural characteristics to different regions: deep trenches have specific width and depth parameters optimized for p-type deep layer formation, while guard ring trenches have different parameters optimized for guard ring layer formation. This local differentiation ensures each layer forms with the desired quality without causing surface irregularities.
2Length of stationary object
If ion implantation and thermal diffusion are used to form a p-type deep layer, then the layer can be formed, but it is difficult to achieve a depth over 1 μm in SiC
Solution Approach 1:
The patent replaces the mechanical/thermal processes of ion implantation and thermal diffusion with the chemical process of embedded epitaxial growth. This substitution enables deep layer formation (over 1 μm) by growing the p-type layer during the epitaxial process rather than attempting to diffuse impurities to such depths, which is extremely difficult in SiC materials.
3Reliability
If the p-type deep layer and p-type guard ring layer are provided individually, then each layer can be optimized, but shape abnormalities and surface irregularities readily occur
Solution Approach 1:
The patent merges the formation processes of the p-type deep layer and p-type guard ring layer into a single embedded epitaxial growth step. By combining these layers and forming them simultaneously in their respective trench structures, the process ensures uniform surface formation while maintaining the individual optimization of each layer's electrical characteristics for proper electric field relaxation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively relaxes the electric field at the bottom of the trench, prevents gate insulating film breakdown, and ensures a desired gate shape, thereby enhancing the breakdown voltage and reducing leakage in SiC semiconductor devices.
Implementation Method 1
a p-type layer is epitaxially grown to fill a trench
Data Source
AI summary
A semiconductor device includes: a substrate having a cell region with a semiconductor element and an outer peripheral region; and a drift layer on the substrate. The semiconductor element includes a base region, a source region, a trench gate structure, a deep layer deeper than a gate trench, a source electrode, and a drain electrode. The outer peripheral region has a recess portion in which the drift layer are exposed, and a guard ring layer. The guard ring layer includes multiple guard ring trenches having a frame shape, surrounding the cell region and arranged on an exposed surface of the drift layer, and a first guard ring in the guard ring trenches. Each of the linear deep trenches has a width equal to a width of each of the linear guard ring trenches.