SiC Trench Gate Oxide Reliability via Shallow Base Region
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Solution Overview
Problem
In high-voltage semiconductor devices with a trench structure, the gate oxide film at the trench bottom is prone to high electric field stress, leading to reliability issues and potential degradation due to the concentration of avalanche current during breakdown, especially when using wide bandgap materials like silicon carbide.
Innovation Solution
The semiconductor device incorporates a trench structure with a shallow region in the base region that is shallower than the deeper base region, allowing for efficient migration of avalanche breakdown holes to the source electrode, reducing the load on the gate oxide film and enhancing reliability by forming a p+-type base region with a shallow region that facilitates easier breakdown and suppresses avalanche current at the trench bottom.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a trench structure is adopted to increase cell density, then current density per unit area is improved, but electric field strength at the trench bottom increases causing gate oxide film degradation
Solution Approach 1:
The patent applies local quality by creating a shallow region with different impurity concentration characteristics within the base region. This shallow region has a different electrical property (higher impurity concentration) compared to the deeper base region, allowing localized control of electric field distribution at the trench bottom while maintaining the overall trench structure benefits for current density enhancement
2Reliability
If a p-type region is formed at the lower portion of the trench to mitigate electric field, then gate oxide film reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges the electric field mitigation function with the existing base region structure by forming a shallow region within the base region. Instead of adding a separate p-type region structure, the invention combines the field mitigation capability into the base region itself through localized impurity concentration modification, thereby reducing device complexity while maintaining reliability improvements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration mitigates the electric field strength at the gate oxide film, secures the breakdown voltage, and effectively suppresses avalanche current, improving the reliability and performance of the semiconductor device.
Implementation Method 1
a shallow region in the base region that is shallower than the deeper base region, allowing for efficient migration of avalanche breakdown holes to the source electrode
Data Source
AI summary
In a semiconductor device having a first p+-type base region, a second p+-type base region, a high-concentration n-type region selectively formed in an n-type silicon carbide epitaxial layer on an n+-type silicon carbide substrate; a p-type base layer formed on the n-type silicon carbide epitaxial layer; an n+-type source region and a p++-type contact region selectively formed in a surface layer of the p-type base layer; and a trench formed penetrating the p-type base layer and shallower than the second p+-type base region, in at least a part of the first p+-type base region, a region is shallower than the second p+-type base region as viewed from an element front surface side.