SiC Trench Gate P-Type Bottom Layer Field Management
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Solution Overview
Problem
Silicon carbide (SiC) semiconductor devices face challenges with high electric field concentrations at the trench gate, leading to gate insulation film damage and increased on-state resistance due to the wide bandgap of SiC, which affects the device's ability to handle high voltages effectively.
Innovation Solution
A silicon carbide semiconductor device with a trench gate structure that includes a P type bottom layer covering the trench bottom and a current dispersion layer between the base region and drift layer, reducing electric field concentration in the gate insulation film and minimizing depletion layer impact on current passage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a trench gate structure is applied to SiC semiconductor device, then the device can control large current, but the gate insulation film at the corner of the trench is easily damaged due to high electric field concentration
Solution Approach 1:
The patent applies local quality by forming a P-type layer specifically at the bottom corner region of the trench where electric field concentration occurs. This localized doping modifies the electrical properties only in the critical area, reducing electric field concentration at the gate insulation film corner without affecting the overall trench gate structure's current control capability.
Solution Approach 2:
The patent changes the electrical parameter (impurity concentration) by forming a P-type layer with specific doping concentration at the trench bottom corner. This parameter change alters the electric field distribution, reducing the peak electric field strength at the gate insulation film corner from 10 MV/cm to below 5 MV/cm, thereby preventing film damage while maintaining device performance.
2Reliability
If a P type layer is formed on the bottom of the trench to reduce electric field concentration, then the gate insulation film is protected, but the depletion layer expands and narrows the current passage, increasing on-state resistance
Solution Approach 1:
The P-type layer is formed locally at the bottom corner region rather than uniformly across the entire trench bottom. This localized approach protects the gate insulation film corner from electric field damage while minimizing the intrusion into the current passage region, thereby reducing the increase in on-state resistance.
Solution Approach 2:
The patent applies partial action by forming the P-type layer only in the necessary corner region rather than covering the entire trench bottom. This partial doping provides sufficient electric field reduction to protect the gate insulation film while leaving the central current passage area largely unaffected, thus minimizing the impact on on-state resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents gate insulation film damage and reduces on-state resistance, enabling the SiC semiconductor device to handle high voltages without breakdown, while maintaining low on-state resistance.
Implementation Method 1
the electric field of 10 MV/cm is concentrated at the trench gate
Implementation Method 2
a depletion layer, which is prepared by applying minus three volts to the P type layer, expands naturally
Implementation Method 3
The MOSFET flows current between the source electrode and the drain electrode through the source region, the current dispersion layer and the drift layer
Data Source
AI summary
A silicon carbide semiconductor device includes: a substrate; a drift layer; a current dispersion layer; a base region; a source region; trenches; a gate insulation film; a gate electrode; a source electrode; a drain electrode; and a bottom layer. The current dispersion layer is arranged on the drift layer, and has a first conductive type with an impurity concentration higher than the drift layer. The bottom layer has a second conductive type, is arranged under the base region, covers a bottom of each trench including a corner portion of the bottom of the trench, and has a depth equal to or deeper than the current dispersion layer.