SiC Trench-Gate Semiconductor Device Optimizing On-Resistance and Withstand Voltage
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Solution Overview
Problem
SiC semiconductor devices with trench-gate structures face a trade-off between low on-resistance and high withstand voltage, making it difficult to reduce device size while maintaining manufacturing yield and cost-effectiveness.
Innovation Solution
The semiconductor device incorporates a specific structure with a conductive-type SiC substrate, epitaxial layer, gate trench, gate insulating film, and conductive layers that satisfy certain relational expressions between on-resistance and withstand voltage, allowing for reduced device size and improved manufacturing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional trench-gate structure is used, then manufacturing is simplified, but on-resistance and withstand voltage cannot be simultaneously optimized
Solution Approach 1:
The patent applies parameter changes by precisely controlling the impurity concentrations in the drift layer (1×10^15 to 1×10^16 cm^-3) and channel layer (1×10^18 to 1×10^19 cm^-3), as well as their thicknesses, to achieve the optimal balance between on-resistance and withstand voltage. This allows the device to break the conventional trade-off relationship.
Solution Approach 2:
The patent uses composite material structure by forming a heterostructure with different conductive types (n-type drift layer, p-type channel layer, n-type source layer) within the epitaxial layer. This composite structure enables simultaneous optimization of electrical properties that cannot be achieved with single-material approaches.
2Productivity
If device size is reduced, then manufacturing yield improves, but on-resistance increases
Solution Approach 1:
The patent reduces on-resistance through parameter changes in the epitaxial layer structure, specifically by optimizing the thickness and impurity concentration of the drift layer and channel layer, which compensates for the reduced active area and maintains low on-resistance even in smaller devices.
Solution Approach 2:
The composite material structure with optimized layer thicknesses and impurity concentrations enables high current density in reduced device areas, allowing smaller devices to maintain low on-resistance while improving manufacturing yield through higher chip counts per substrate.
Data Source
AI summary
The present invention provides a semiconductor device that can achieve both low on-resistance and high withstand voltage, while reducing the device size, improving the manufacturing yield, and reducing the cost. The semiconductor device 1 includes a substrate 5, an epitaxial layer 6 formed on the substrate 5 and formed with a gate trench 11, a gate insulating film 17 formed on the side surface 14 and the bottom surface 15 of the gate trench 11, a gate electrode 20 embedded in the gate trench 11 and opposed to the epitaxial layer 6 with the gate insulating film 17 therebetween, and a source layer 25, a channel layer 26, and a drift layer 27 formed in this order from a first surface to a second surface of the epitaxial layer 6, in which the on-resistance Ron represented by a variable “y” and the withstand voltage Vb represented by a variable “x” functionally satisfy the following relational expression (1):y≤9×10−7x2−0.0004x+0.7001 (1).