SiC Trench Gate Device Hydrogen Etching Control
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Solution Overview
Problem
Conventional silicon carbide semiconductor devices with trench gate structures face increased channel resistance due to excess carbon during thermal oxidation and disrupted crystal arrangement from fluorine-based etching, leading to inefficiencies in high-voltage applications.
Innovation Solution
A silicon carbide semiconductor device and manufacturing method involving a hydrogen etching process at temperatures between 1300°C and 1500°C, which suppresses silicon and carbon diffusion, allowing for fine etching control and reducing trench width, thereby minimizing channel resistance and leak points.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If thermal oxidation is used to form gate insulating film, then gate insulating film can be formed, but excess carbon is generated and channel resistance increases
Solution Approach 1:
The patent changes the temperature parameter of the oxidation process to 1300-1500°C, which is lower than conventional thermal oxidation temperatures. This parameter change suppresses carbon diffusion and prevents excess carbon generation at the interface, while still enabling gate insulating film formation with acceptable electrical characteristics
Solution Approach 2:
The patent uses a composite approach by forming the gate insulating film through oxidation in a controlled temperature environment, combining the benefits of oxide film formation with suppressed carbon contamination. The process creates a cleaner interface between the gate insulating film and silicon carbide substrate
2Manufacturing precision
If fluorine-based etching is used to form trenches, then trenches can be formed, but crystal arrangement is disrupted and channel resistance increases
Solution Approach 1:
The patent changes the etching temperature parameter to 1300-1500°C and uses hydrogen-based etching instead of fluorine-based etching. This parameter and chemical composition change enables precise trench formation while suppressing silicon diffusion and maintaining crystal arrangement stability
Solution Approach 2:
The patent substitutes fluorine-based chemical etching with hydrogen-based etching. This chemical substitution eliminates the harmful effects of fluorine on crystal structure while maintaining effective trench formation capability through controlled silicon removal
3Object-generated harmful factors
If trench width is reduced to lower channel resistance, then channel resistance decreases, but etching control becomes more difficult
Solution Approach 1:
The patent optimizes the etching temperature to 1300-1500°C, which provides ideal kinetics for silicon removal while maintaining crystal structure stability. This temperature parameter enables precise control of etching depth and width, allowing narrow trench formation with excellent manufacturing precision and suppressed silicon diffusion
Solution Approach 2:
The substitution of hydrogen-based etching for fluorine-based etching provides better etching control characteristics. The hydrogen etching process offers more predictable etching rates and better sidewall profile control, enabling precise fabrication of narrow trenches with minimal crystal damage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The hydrogen etching process reduces trench width and channel resistance, enhancing the reliability and performance of silicon carbide semiconductor devices for high-voltage applications by eliminating excess carbon and thermal oxidation-related issues.
Implementation Method 1
hydrogen etching process at temperatures between 1300°C and 1500°C, which suppresses silicon and carbon diffusion
Implementation Method 2
hydrogen annealing treatment at high temperature
Data Source
AI summary
A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate of a first conductivity type, a first silicon carbide semiconductor layer of the first conductivity type, a second silicon carbide semiconductor layer of a second conductivity type, a first silicon carbide semiconductor region of the first conductivity type, a trench, and a gate electrode on a gate insulating film. Between the gate insulating film and any one among the first silicon carbide semiconductor layer, the second silicon carbide semiconductor layer, and the first silicon carbide semiconductor region is an interface section where a concentration of oxygen varies, the interface section having closer to the gate insulating film than to the any one among the first silicon carbide semiconductor layer, the second silicon carbide semiconductor layer, and the first silicon carbide semiconductor region, a region where a rate of increase of the oxygen included in the interface section is greatest.