SiC Trench JFET Heterojunction Gate Without High-Temperature Implant
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Solution Overview
Problem
Conventional silicon carbide-based power semiconductor devices require high-temperature implantation and activation anneal processes for forming gate contact regions, which are costly and complex.
Innovation Solution
The use of a heterojunction gate structure formed via deposition methods, such as sputtering, eliminates the need for high-temperature implants by creating a PN junction between a p-type non-SiC material and the channel layer, allowing for the formation of a heterojunction gate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-temperature implantation and activation anneal processes are used to form gate contact regions, then the device performance is improved, but the manufacturing complexity and cost increase
Solution Approach 1:
The patent changes the formation method of the gate contact region from high-temperature implantation and annealing to a lower-temperature deposition process. The heterojunction gate structure is formed by depositing a p-type semiconductor material layer on the n-type channel layer, eliminating the need for high-temperature processing while maintaining device performance.
Solution Approach 2:
The patent replaces the thermal processing mechanism (high-temperature implantation and annealing) with a deposition mechanism. The gate contact region is formed by depositing a heterojunction material layer, substituting the mechanical/thermal process with a material deposition process that achieves the same electrical function at lower temperatures.
2Reliability
If high-temperature implantation and activation anneal processes are used to form gate contact regions, then the device performance is improved, but the manufacturing cost increases
Solution Approach 1:
The patent changes the processing temperature parameter from high-temperature (requiring implantation and annealing) to lower-temperature deposition. This parameter change reduces manufacturing cost by eliminating expensive high-temperature processing steps while maintaining the electrical performance of the gate contact region through the heterojunction structure.
3Ease of manufacture
If a heterojunction gate structure is used, then the manufacturing process is simplified, but the device structure becomes more complex
Solution Approach 1:
The patent employs composite material structure by forming a heterojunction between p-type semiconductor material layer and n-type channel layer. This composite structure achieves simplified manufacturing through deposition processes while the resulting heterojunction gate structure represents a controlled structural complexity that enables the manufacturing simplification.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process, reduces costs, and enhances the performance of silicon carbide JFET devices by obviating the need for high-temperature implantation and anneal steps.
Implementation Method 1
The use of a heterojunction gate structure formed via deposition methods, such as sputtering
Data Source
AI summary
A semiconductor device includes a drift layer including silicon carbide and having a first conductivity type, a channel layer on the drift layer, the channel layer including silicon carbide and having the first conductivity type, and a source layer on the channel layer, the source layer including silicon carbide and having the first conductivity type. The device includes first and second trenches extending through the source layer and at least partially into the channel layer. The first and second trenches define a mesa therebetween having a mesa sidewall adjacent the channel layer. A heterojunction layer is in the first trench. The heterojunction layer includes a semiconductor material having a second conductivity type opposite the first conductivity type, wherein the heterojunction layer forms a PN heterojunction with silicon carbide.