Silicon Carbide Trench Layout for Lower ON Resistance
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Solution Overview
Problem
Conventional silicon carbide semiconductor devices have limitations in reducing cell pitch and enhancing channel width density, leading to increased ON resistance due to the sequential arrangement of n+-type base regions, p++-type contact regions, and n+-type base regions between trenches, which restricts further miniaturization and performance enhancement.
Innovation Solution
The semiconductor device incorporates n+-type source regions and p++-type contact regions arranged between trenches in a stripe pattern, with intervals to reduce their widths and prevent overlapping, allowing for reduced cell pitch and enhanced channel width density, thereby decreasing ON resistance and improving gate reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If n+-type base regions, p++-type contact regions, and n+-type base regions are sequentially arranged between trenches, then the device structure is formed according to conventional design, but the cell pitch cannot be reduced further and channel width density cannot be enhanced
Solution Approach 1:
The patent merges the n+-type base region and p++-type contact region into a single integrated doped region. This consolidation eliminates the need for sequential arrangement of separate regions, thereby reducing cell pitch while maintaining or enhancing channel width density. The merged region performs both the base function and contact function simultaneously.
Solution Approach 2:
The patent transitions from a one-dimensional sequential arrangement of doped regions to a two-dimensional configuration where doped regions are positioned at specific locations including trench bottoms and sidewalls. This spatial redistribution in multiple dimensions enables reduced cell pitch while preserving functional requirements.
2Ease of manufacture
If conventional sequential arrangement of doped regions is used, then device structure is simple to manufacture, but ON resistance increases due to limited channel width density
Solution Approach 1:
The patent applies different doping characteristics to different locations within the semiconductor structure. Specifically, n+-type doped regions are positioned at trench bottoms and sidewalls with optimized local concentrations, creating high channel width density in critical areas while maintaining manufacturability through targeted doping rather than uniform sequential arrangement.
3Manufacturing precision
If n+-type source regions and p++-type contact regions are arranged in stripe pattern with intervals, then cell pitch is reduced and channel width density is enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the doped regions into discrete n+-type source regions and p++-type contact regions arranged in a stripe pattern with controlled intervals. This segmentation enables precise control over cell pitch and channel width density, allowing optimization of electrical performance while maintaining manufacturability through systematic spatial distribution.
Data Source
AI summary
A semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, second semiconductor regions of the second conductivity type, gate insulating films, gate electrodes, an insulating film, first electrodes, a second electrode, and trenches. The first semiconductor regions and the second semiconductor regions are periodically disposed apart from one another in a first direction in which the trenches extend in a stripe pattern.