SiC Trench Gate Metal Layer Reduces On-Resistance
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Solution Overview
Problem
Current semiconductor devices with trench gate structures face challenges in reducing on-resistance while maintaining breakdown voltage and reliability, particularly due to the limitations of p-type SiC regions and high-temperature processing which can deteriorate gate insulating films and introduce impurity diffusion issues.
Innovation Solution
The implementation of a metal layer with a work function of 6.5 eV or more, specifically 3C-SiC in a metal state, within the trench structure replaces the p-type SiC region, reducing the unit cell pitch and eliminating the need for p-type SiC for electric field reduction, thereby decreasing on-resistance and enhancing reliability by using low-temperature growth to stabilize the 3C-SiC structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a trench gate structure with p-type SiC regions is used to reduce on-resistance, then on-resistance decreases, but the unit cell pitch increases and device complexity increases
Solution Approach 1:
The invention extracts and removes the p-type SiC regions from the trench gate structure, replacing them with a metal layer. This simplifies the device structure by eliminating unnecessary components while maintaining the on-resistance reduction benefit through the metal layer's electrical field shielding effect
Solution Approach 2:
The invention changes the material parameter in the trench from semiconductor (p-type SiC) to metal, utilizing the metal's higher conductivity and electrical field shielding properties to achieve lower on-resistance without requiring the complex p-type SiC region structure
2Loss of energy
If high-temperature processing is used to form p-type SiC regions, then on-resistance decreases, but gate insulating film breakdown and impurity diffusion occur
Solution Approach 1:
The invention changes the processing temperature parameter from high-temperature to low-temperature formation, using low-temperature metal layer deposition instead of high-temperature p-type SiC region formation, thereby avoiding gate insulating film breakdown and impurity diffusion while achieving comparable on-resistance reduction
Solution Approach 2:
The invention substitutes the high-temperature thermal processing mechanism with a low-temperature metal deposition mechanism, replacing the thermally-driven p-type SiC formation process with a physical vapor deposition or similar low-temperature metal layer formation process
3Strength
If p-type SiC regions are used for electric field reduction, then breakdown voltage is maintained, but the structure becomes more complex and occupies more space
Solution Approach 1:
The invention extracts and removes the p-type SiC regions that occupy space in the structure, replacing them with a thin metal layer that provides equivalent or superior electrical field shielding, thereby reducing the unit cell pitch while maintaining breakdown voltage
Solution Approach 2:
The invention uses a composite structure combining the metal layer with the gate insulating film and gate electrode, creating a simplified composite system that achieves both breakdown voltage maintenance and space reduction compared to the p-type SiC region structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a semiconductor device with lower on-resistance and improved reliability by reducing the electric field concentration at trench corners and suppressing gate insulating film breakdown, while maintaining high breakdown voltage and minimizing impurity diffusion-related issues.
Implementation Method 1
a metal layer provided between the one of the second SiC regions and the other one of the second SiC regions neighbouring the one of the second SiC regions, the metal layer having a work function of 6.5 eV or more
Implementation Method 2
The implementation of a metal layer with a work function of 6.5 eV or more, specifically 3C-SiC in a metal state, within the trench structure replaces the p-type SiC region, reducing the unit cell pitch and eliminating the need for p-type SiC for electric field reduction, thereby decreasing on-resistance
Implementation Method 3
enhancing reliability by using low-temperature growth to stabilize the 3C-SiC structure
Data Source
AI summary
A semiconductor device of an embodiment includes an SiC layer having a first and a second plane, an n-type first SiC region in the SiC layer, p-type second SiC regions between the first SiC region and the first plane, n-type third SiC regions between the second SiC regions and the first plane, a gate electrode provided between two p-type second SiC regions, a gate insulating film provided between the gate electrode and the second SiC regions, a metal layer provided between two p-type second SiC regions, and having a work function of 6.5 eV or more, and a first electrode electrically connected to the metal layer, and a second electrode, the SiC layer provided between the first electrode and the second electrode, and a part of the first SiC region is disposed between the gate insulating film and the metal layer.