SiC Trench MOSFET Embedded Layer Alignment
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional silicon carbide (SiC) trench MOSFETs face issues with channel mobility degradation due to ion implantation and alignment precision degradation caused by epitaxial growth, leading to increased resistance and potential gate oxide film breakdown.
Innovation Solution
A silicon carbide semiconductor device with a drift layer, epitaxial layer, and embedded layer structure, where the trench is formed with a striped planar pattern parallel to the substrate off-direction, and the embedded layer is longer than the channel layer to reduce marker pattern deformation and prevent gate oxide film breakdown, while maintaining effective edge termination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If ion implantation is used to form the channel layer, then the manufacturing process is simpler, but channel mobility is degraded due to crystal damage and surface roughness
Solution Approach 1:
The patent changes the formation method parameter from ion implantation to epitaxial growth, and optimizes epitaxial growth parameters (temperature, pressure, gas flow) to achieve high channel mobility without crystal damage. The channel layer is formed by controlling epitaxial growth conditions to maintain crystal integrity while achieving desired doping concentrations.
2Manufacturing precision
If epitaxial growth is used to form the channel layer, then channel mobility is improved, but marker pattern deformation occurs causing alignment precision degradation
Solution Approach 1:
The patent performs preliminary actions by forming the p-type embedded layer with specific dimensions and position before epitaxial growth, and designing marker patterns that account for expected deformation. The embedded layer structure is prepared in advance to provide reference features that remain stable during subsequent processing steps.
Solution Approach 2:
The patent introduces asymmetric design in the p-type embedded layer structure, where the embedded layer extends beyond the channel layer on one side. This asymmetric configuration creates stable reference features that are less susceptible to alignment errors during epitaxial growth, allowing the marker pattern to maintain functionality despite deformation.
3Reliability
If the p-type embedded layer is positioned at the trench bottom to protect the oxide film, then gate oxide film breakdown is prevented, but alignment shifting occurs between the embedded layer and trench bottom
Solution Approach 1:
The patent introduces the p-type embedded layer as an intermediary structure between the drift layer and the gate oxide film. This embedded layer serves as a protective mediator that prevents direct contact between the trench bottom and the oxide film, reducing electric field concentration and preventing breakdown while providing a stable alignment reference.
Solution Approach 2:
The patent solves the alignment problem by extending the p-type embedded layer in the depth dimension beyond the channel layer. This dimensional extension creates an overlapping region that ensures alignment between the embedded layer and trench bottom, compensating for any lateral misalignment that may occur during manufacturing.
4Device complexity
If the trench is formed perpendicular to the substrate surface, then the device structure is simplified, but step bunching effects and dielectric breakdown increase
Solution Approach 1:
The patent applies curvature by forming the trench at an angle (e.g., 80-85 degrees from the substrate surface) rather than perpendicular. This angled configuration reduces step bunching effects at the trench bottom and distributes electric field more uniformly, preventing dielectric breakdown while maintaining relatively simple device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the deformation of the marker pattern, prevents shifting of the p-type embedded layer and trench bottom, and enhances the breakdown voltage of the gate oxide film, maintaining low resistance and effective edge termination.
Implementation Method 1
when the channel layer is formed by epitaxial growth, although the channel mobility is improved
Data Source
AI summary
A silicon carbide semiconductor device, including a silicon carbide substrate, a drift layer provided on a front surface of the silicon carbide substrate, an embedded layer selectively provided in a surface layer of the drift layer, an epitaxial layer provided on the drift layer, a channel layer provided on the epitaxial layer, a source region selectively provided in a surface layer of the channel layer, a trench penetrating the source region and the channel layer and reaching the epitaxial layer, a gate electrode provided in the trench via a gate insulating film, a source electrode in contact with the channel layer and the source region, and a drain electrode provided on a rear surface of the silicon carbide substrate. The embedded layer is arranged underneath the trench in a depth direction. A longitudinal direction of the trench, which is perpendicular to the depth direction, is parallel to the off-direction of the silicon carbide substrate.