SiC Trench MOSFET Base Layer Thickness Optimization
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Solution Overview
Problem
Trench MOSFETs using silicon carbide semiconductor devices exhibit high leakage currents due to threading dislocations, which increase ON-resistance and power loss, and existing methods to reduce leakage current either fail to adequately lower it or raise the threshold voltage.
Innovation Solution
A silicon carbide semiconductor device with a thicker p-type epitaxial base layer (≥8 μm) is designed to reduce the concentration of ion species and point defects along dislocations, preventing conductive paths between the source and drain, and featuring narrower second trenches reaching the drift layer to minimize channel resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a thinner base layer is used, then channel resistance decreases and ON-resistance is reduced, but leakage current increases due to higher concentration of ion species and point defects along dislocations
Solution Approach 1:
The patent applies parameter changes by optimizing the base layer thickness to a specific range (5 μm to 15 μm, preferably 8 μm to 12 μm). This parameter optimization balances two opposing effects: reducing channel resistance by keeping the base layer thin enough, while preventing excessive leakage current by maintaining it thick enough to reduce ion species and point defect concentration along dislocations. This quantitative parameter control resolves the contradiction between ON-resistance and leakage current.
2Object-generated harmful factors
If existing methods are used to reduce leakage current, then leakage current decreases, but threshold voltage increases
Solution Approach 1:
The patent resolves this contradiction through precise parameter control of base layer thickness within the 5-15 μm range. By controlling the thickness parameter, the patent achieves leakage current reduction while maintaining threshold voltage within the acceptable range of 4V to 7V. This parameter optimization prevents the threshold voltage increase that occurs with conventional leakage reduction methods.
3Ease of manufacture
If threading dislocations are present, then manufacturing is easier, but leakage current increases due to conductive paths formed by ion species and point defects
Solution Approach 1:
The patent applies parameter changes by controlling base layer thickness to compensate for the presence of threading dislocations. By maintaining the base layer thickness within 5-15 μm, the patent reduces the concentration of ion species and point defects along dislocation paths, thereby reducing leakage current while accepting the ease of manufacturing with standard dislocation densities in silicon carbide substrates.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces leakage current while maintaining an appropriate threshold voltage, improving yield rate and reducing ON-resistance, as demonstrated by achieving an 80% yield rate with acceptable leakage current and high avalanche breakdown voltage.
Implementation Method 1
a concentration of ion species or point defects running along dislocations in the base layer is so low that regions surrounding the dislocations do not conduct current due to the ion species or the point defects
Implementation Method 2
gate oxide films 108 arranged on the sidewalls of the trenches 107
Data Source
AI summary
A silicon carbide semiconductor device includes an n-type drift layer and a p-type epitaxial base layer deposited on an n-type silicon carbide substrate, as well as first trenches and second trenches. N-type source regions are formed in the surface layer of the p-type epitaxial base layer, in the sidewalls of the first trenches, and in the bottoms of the first trenches. The thickness of the p-type epitaxial base layer is set so that a concentration of ion species or point defects running along dislocations in the p-type epitaxial base layer is so low that regions surrounding the dislocations do not conduct current due to the ion species or the point defects.