SiC Trench MOSFET Shielding Layer for Gate Breakdown Protection
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Solution Overview
Problem
Conventional silicon carbide (SiC) MOSFET devices face issues with high electrical field-induced gate dielectric breakdown, poor tolerance to harsh electrostatic environments, and limited anti-surge and overvoltage protection, leading to reliability concerns and complex external protection circuits.
Innovation Solution
The silicon carbide MOSFET device incorporates an epitaxial wafer with a trench gate structure, a well region comprising multiple layers, and a shielding layer to protect the gate, along with a JFET structure that adjusts ON-resistance and provides self-locking protection, enhancing voltage endurance and reducing switching losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional silicon carbide MOSFET devices are used, then basic MOSFET functionality is achieved, but voltage endurance is poor and gate dielectric breakdown occurs under high electrical fields
Solution Approach 1:
A shielding layer with the same polarity as the well region is introduced as an intermediary protective structure between the high electrical field environment and the gate dielectric. This shielding layer acts as a mediator that redistributes and reduces the electrical field stress on the gate dielectric, preventing breakdown while maintaining basic MOSFET functionality.
Solution Approach 2:
The shielding layer is positioned beforehand to cushion and absorb the impact of high electrical fields before they can reach the gate dielectric. This preemptive protective structure reduces the electrical field intensity in advance, preventing gate dielectric breakdown under surge voltage conditions.
2Reliability
If conventional silicon carbide MOSFET devices are used, then standard operation is achieved, but tolerance to harsh electrostatic environments is poor
Solution Approach 1:
The shielding layer serves as an intermediary protective barrier between the electrostatic environment and the sensitive gate dielectric. It mediates the electrostatic stress by providing a conductive path and reducing the field intensity, thereby improving tolerance to harsh electrostatic environments.
3Reliability
If conventional silicon carbide MOSFET devices are used, then basic switching function is achieved, but anti-surge and overvoltage protection is limited
Solution Approach 1:
The shielding layer acts as an intermediary protective structure that intercepts and redistributes surge voltage before it reaches the gate dielectric. It provides a conductive path for surge current and reduces the voltage stress, enhancing anti-surge and overvoltage protection capabilities.
Solution Approach 2:
The shielding layer is positioned beforehand to cushion the impact of surge voltages. It absorbs and redistributes the surge energy before it can cause damage to the gate dielectric, providing inherent overvoltage protection without requiring external protection circuits.
4Device complexity
If conventional silicon carbide MOSFET devices are used, then simple structure is maintained, but external protection circuits are required
Solution Approach 1:
The protective function previously requiring external circuits is merged into the device structure itself through the shielding layer. This integration combines the MOSFET's switching function with inherent overvoltage protection, eliminating the need for separate external protection circuits and reducing overall system complexity.
Solution Approach 2:
The MOSFET device provides its own protection against surge and overvoltage through the integrated shielding layer. The device serves itself by having the shielding layer automatically redistribute and absorb harmful electrical stress, eliminating the need for external protection circuits and reducing switching losses.
Data Source
AI summary
A SiC MOSFET device and a method for manufacturing the same. The SiC MOSFET device comprises: an epitaxial wafer comprising a semiconductor substrate and epitaxial layers on a surface of the semiconductor substrate; and a well region, a source region, and a trench gate, which are in the epitaxial layers. The trench gate comprises a gate disposed in a trench at a surface of the epitaxial layers. The source region surrounds the trench. The well region comprises a first layer, a second layer, and a third layer. A bottom of the trench is disposed higher than the first layer and lower than the third layer. The third layer surrounds the trench. Doped region(s) are disposed in the epitaxial layers and beneath the trench, and the first layer surrounds each doped region. A shielding layer is disposed in a part of the epitaxial layers beneath the trench.