SiC Trench MOSFET Double Gate Structure for Parasitic BJT Control
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Solution Overview
Problem
Commercially available power field effect transistors based on silicon carbide have high on-state resistance due to parasitic junction field effect transistors and bipolar junction transistors, which limit current density and increase the risk of latchup, a condition that can destroy the device.
Innovation Solution
A power semiconductor device with a trench design featuring a double gate structure and a specific three-dimensional layout that reduces the double gate distance, enhancing electrostatic gate control, and includes body contact regions to shorten the parasitic bipolar junction transistor, allowing for higher on-state current and reduced short-channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If p-type implantations are used to form gates in planar VDMOS, then the device structure is simple to manufacture, but the parasitic JFET regions increase the on-state resistance
Solution Approach 1:
The patent transitions from a planar two-dimensional structure to a three-dimensional trench structure. The channel is formed at the bottom of trenches etched into the semiconductor substrate, allowing the current flow path to be separated from the gate control regions. This dimensional change eliminates the parasitic JFET effect while maintaining manufacturing feasibility through standard trench etching and filling processes.
Solution Approach 2:
The device is divided into multiple independent trench structures arranged in an array. Each trench acts as an independent FET cell with its own gate, channel, and drain regions. This segmentation allows the current to flow through multiple parallel paths at the trench bottoms, reducing the overall on-state resistance without requiring complex planar doping patterns.
2Reliability
If the body region is connected to source metallization to short the parasitic BJT, then the device can operate without latchup, but the additional p+ doping increases the complexity of the device structure
Solution Approach 1:
The patent extracts and eliminates the parasitic BJT structure by separating the body region from the source region. In the trench MOSFET design, the body region forms the channel at the trench bottom and is naturally isolated from the source contact, which sits on the drift region. This extraction removes the base-emitter junction that causes latchup, eliminating the need for additional p+ body contact regions and simplifying the overall device structure.
3Power
If current density is increased in planar VDMOS, then the power handling capability improves, but the parasitic JFET regions limit the maximum achievable current density
Solution Approach 1:
The current flow is redirected from a planar surface path to a vertical path through the trench structures. Current enters the drift region, flows vertically through the depleted drift layer, and exits through the drain contact. This three-dimensional current path eliminates the pinching effect of parasitic JFET gates, enabling higher current densities and improved power handling capability.
Solution Approach 2:
The drift region is pre-doped with a controlled resistivity to optimize the balance between breakdown voltage and on-state resistance. The trench structures are formed with specific geometries (depth, width, spacing) that are predetermined to achieve optimal electric field distribution and current carrying capacity before the device is operated, allowing maximum current density to be achieved without latchup or excessive conduction loss.
Data Source
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AI summary
A power semiconductor device (1) comprises plurality of vertical field effect transistor cells (10) arranged in a plurality of parallel rows, each row including vertical field effect transistor cells (10) arranged along a first direction (x), wherein in each vertical field effect transistor cell (10) a body region (5a) is surrounded by the gate layer from two lateral surfaces (16) of the body region (5a) opposite to each other. In each row of vertical field effect transistor cells (10) the body regions (5a) are separated from each other in the first direction (x) by first gate regions (7a) of the gate layer (7), each first gate region (7a) penetrating through the body layer (5), so that in each row of vertical field effect transistor cells (10) the first gate regions (7a) alternate with the body regions (5a) along the first direction (x). The first gate regions (7a) within each row of vertical field effect transistor cells (10) are connected with each other by second gate regions (7b) extending across the body regions (5a) of the respective vertical field effect transistor cells (10) in the first direction (x). The first gate regions (7a) and the second gate regions (7b) form continuous gate strips extending with its longitudinal axis in the first direction (x). A source electrode (65) is formed on the source layer (6) to form a first ohmic contact to the source layer (6) between each pair of adjacent gate strips. The whole top surface (17') of the body region (5a') facing away from the substrate layer (4) is in direct contact with the gate insulation layer (8).