SiC Trench MOSFET Structure for Lower On-Resistance and Gate Reliability
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Solution Overview
Problem
Existing silicon-based MOSFETs face challenges in reducing on-resistance and improving reliability and switching loss due to their physical properties, which silicon carbide-based MOSFETs aim to address.
Innovation Solution
A trench gate type vertical MOSFET using silicon carbide with a specific trench and gate electrode structure, including electric field relaxation regions and connection regions, to enhance channel area, reduce on-resistance, and improve gate insulating layer reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon-based MOSFETs are used, then manufacturing maturity and ease of manufacture are maintained, but on-resistance cannot be sufficiently reduced and reliability at high temperatures is limited
Solution Approach 1:
The patent changes the material parameter from silicon to silicon carbide, which fundamentally alters the physical properties including band gap, breakdown field strength, and thermal conductivity. This material parameter change enables high-temperature operation and reduced on-resistance while maintaining manufacturing feasibility through established SiC fabrication processes
Solution Approach 2:
The patent employs a composite structure combining silicon carbide drift region with specific doping configurations (n-type and p-type regions) to create a MOSFET that leverages the superior properties of SiC while using conventional semiconductor fabrication techniques for the gate and contact structures
2Reliability
If conventional trench gate structures are used, then manufacturing simplicity is maintained, but channel area is insufficient and on-resistance remains high
Solution Approach 1:
The patent transitions from a planar gate structure to a vertical trench gate structure, utilizing the third dimension (depth) to increase the effective channel area. The trench extends vertically into the drift region, allowing the gate to control a larger channel area without increasing the device footprint, thereby reducing on-resistance
Solution Approach 2:
The patent segments the gate structure into multiple trenches rather than using a single continuous gate, which allows for optimized electric field distribution and reduced peak fields at the gate edges. This segmentation also facilitates manufacturing by enabling standard trench formation processes to be applied repeatedly
3Speed
If gate insulating layers are made thinner to reduce capacitance, then switching speed improves, but reliability of the gate insulating layer deteriorates
Solution Approach 1:
The patent uses a composite gate insulating layer structure combining silicon oxide and silicon nitride layers. The silicon oxide provides good interface quality with silicon carbide, while the silicon nitride layer provides high dielectric strength and reliability. This composite structure achieves both low capacitance for fast switching and high reliability for long-term operation
Solution Approach 2:
The patent changes the dielectric material parameters by selecting silicon nitride with its high dielectric constant and superior breakdown characteristics. This material parameter change allows the gate insulating layer to maintain thin dimensions for fast switching while achieving the required reliability through the material's inherent properties
4Reliability
If electric field relaxation regions are not provided, then device structure is simpler, but switching loss increases and reliability deteriorates
Solution Approach 1:
The patent incorporates electric field relaxation regions (n-type and p-type) that are pre-formed in the drift region before final device operation. These regions are designed to actively manage electric field distribution during switching transitions, preemptively reducing peak fields and minimizing switching losses before they can cause damage or excessive power dissipation
Data Source
AI summary
A semiconductor device according to an embodiment includes: a silicon carbide layer having a first surface and second surface parallel to a first direction and a second direction perpendicular to the first direction; a first trench and second trench extending in the first direction; an n-type first region in the silicon carbide layer; a p-type second region between the first region and the first surface in the silicon carbide layer; an n-type third region between the second region and the first surface in the silicon carbide layer; a p-type sixth region between the first region and the first trench in the silicon carbide layer; and a p-type eighth region located between the second region and the first trench, between the third region and the first trench, and in contact with the sixth region in the silicon carbide layer. The eighth regions are repeatedly disposed in the first direction.