SiC Trench MOSFET Layout for Lower On-Resistance and Gate Field Shielding
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Solution Overview
Problem
The silicon carbide (SiC) MOSFET devices with a trench gate structure face a contradiction between channel region resistance and junction field effect transistor (JFET) region resistance, leading to increased total on-resistance and reduced performance, along with reliability issues due to high electric field stress on the gate dielectric layer.
Innovation Solution
The semiconductor device incorporates a trench structure with a second trench connecting first trenches, allowing for a tighter arrangement and higher channel density, and includes a first P-type semiconductor region connected to the source to shield the gate dielectric layer from high electric fields, reducing on-resistance and improving robustness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the spacing between trench gate structures is reduced to decrease cell size and increase channel density, then the resistance of the channel region is reduced, but the through-current width of the JFET region is reduced, leading to an increase in the resistance of the JFET region and an increase in total on-resistance
Solution Approach 1:
The device is divided into multiple cells with trench gate structures arranged in a grid pattern, allowing independent optimization of each cell's dimensions while maintaining overall device performance
Solution Approach 2:
The patent optimizes specific parameters including trench gate spacing (5-15 μm), trench depth (5-15 μm), and JFET region width (2-5 μm) to achieve the right balance between channel density and JFET region current capacity, reducing total on-resistance while maintaining low cell size
2Length of moving object
If the trench gate structure is used to increase channel density and reduce cell size, then the channel region resistance is reduced, but the gate dielectric layer at the bottom and corner of the trench gate structure bears extremely high electric field strength, causing reliability failure
Solution Approach 1:
A field plate structure is introduced as an intermediary element that extends over the gate dielectric layer at the trench bottom and corners, distributing the electric field stress and preventing direct high-field exposure of the gate dielectric, thereby enhancing reliability while maintaining the compact trench gate structure
Solution Approach 2:
The field plate is designed to preemptively shield the gate dielectric layer from high electric field stress before breakdown can occur, creating a protective buffer zone that prevents reliability failures during device operation
Data Source
AI summary
A semiconductor device includes an N-type semiconductor substrate, an epitaxial layer, a trench structure, a gate, an interlayer dielectric layer, a source, and a drain. The epitaxial layer includes a first P-type semiconductor region. A bottom of the trench structure is in contact with the first P-type semiconductor region. The trench structure includes a plurality of first trenches and one second trench. The first trenches extend in a first direction. The second trench and each of the plurality of first trenches are disposed in a cross manner and communicate with each other. The interlayer dielectric layer covers the gate and has a contact hole that extends in a second direction. The source is disposed at the interlayer dielectric layer. The source is in contact with the source region through the contact hole and is connected to the first P-type semiconductor region.