SiC Trench Gate MOSFET Channel Resistance Reduction
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Solution Overview
Problem
Trench gate-type semiconductor devices using silicon carbide face challenges in reducing channel resistance, which is essential for achieving lower ON resistance, even when damage from ion implantation is minimized.
Innovation Solution
Reducing the surface roughness of the side wall surface of the trench to less than 1.0 nm RMS, aligning the side wall surface with specific crystal planes like the (0-11-2) plane, and controlling the angle with respect to the {01-12} plane to minimize channel resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If ion implantation is used to form the channel region, then the channel region can be created, but damage on the channel formation surface increases leading to higher channel resistance
Solution Approach 1:
The patent replaces the mechanical ion implantation process with a chemical field-effect approach. By applying a voltage to the gate electrode, an electric field is created that induces carrier accumulation in the channel region, forming the conductive path without physical impact or surface damage.
Solution Approach 2:
The gate insulating film serves as an intermediary between the gate electrode and the semiconductor substrate. It transmits the electric field from the gate to the channel region while protecting the channel formation surface from direct contact with ions or other harmful factors.
2Productivity
If conventional trench gate structure is used, then miniaturization is achieved, but channel resistance remains high limiting further ON resistance reduction
Solution Approach 1:
The patent changes the electrical parameters by applying specific voltages to the gate electrode, which modulates the carrier concentration in the channel region. This allows dynamic control of channel resistance without changing the physical dimensions of the trench gate structure.
Solution Approach 2:
The patent creates a localized high-carrier-concentration region at the channel formation surface through the electric field effect. This local quality enhancement reduces channel resistance specifically at the critical interface region without affecting other parts of the device.
Data Source
Figure 1
Figure 2
Figure 3~5
AI summary
A MOSFET (1) includes: a substrate (10) having a trench (19) formed therein and made of silicon carbide, the trench (19) being opened on one main surface (10A) side and having a side wall surface (19A); a gate insulating film (21) formed on the side wall surface (19A) in contact therewith; and a gate electrode (23) formed on the gate insulating film (21) in contact therewith, wherein a square region with each side of 100 nm in the side wall surface (19A) has a surface roughness of not more than 1.0 nm in RMS.