SiC Trench MOSFET Two-Layer N-Type Structure
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Solution Overview
Problem
Conventional power semiconductor devices, such as trench-type MOSFETs, face limitations in achieving both high current density and high switching speed due to the short channel effect and increased ON resistance, which restricts their performance and efficiency, especially when using silicon as a semiconductor material.
Innovation Solution
The semiconductor device employs a two-layer n-type semiconductor structure with a lower impurity concentration ratio between the n−-type layers to suppress the short channel effect and reduce ON resistance, featuring a first conductivity-type semiconductor layer with a lower concentration, a second conductivity-type semiconductor layer with a higher concentration, and a third conductivity-type semiconductor layer with an even higher impurity concentration, embedded with an oxide film and a gate electrode in trenches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the channel length is reduced to lower ON resistance, then the ON resistance decreases, but the short channel effect increases and breakdown voltage control becomes difficult
Solution Approach 1:
The patent applies local quality by creating a multi-layered semiconductor structure with different impurity concentrations in specific regions. The first conductivity-type semiconductor layer has a first impurity concentration, the second conductivity-type semiconductor layer has a second impurity concentration, and the third conductivity-type semiconductor layer has a third impurity concentration. This localized variation in impurity concentration allows the channel length to be reduced for lower ON resistance while maintaining proper breakdown voltage control through the graded structure.
Solution Approach 2:
The patent employs parameter changes by systematically varying the impurity concentration across different layers and regions. The relationship between the impurity concentrations is specifically controlled: the second impurity concentration is lower than the first, and the third impurity concentration is higher than the second. This parameter optimization enables simultaneous achievement of low ON resistance and reliable breakdown voltage control.
2Ease of manufacture
If silicon is used as the semiconductor material, then the device structure is simple and manufacturing is mature, but the performance reaches the theoretical limit and cannot achieve both large current and high speed
Solution Approach 1:
The patent uses composite materials by combining multiple semiconductor layers with different conductivity types and impurity concentrations. This composite structure enables the device to achieve both large current capability and high-speed switching characteristics that cannot be obtained with conventional single-material silicon devices, while still benefiting from mature silicon manufacturing processes.
Data Source
AI summary
An active region through which current flows in a semiconductor device includes an n−-type silicon carbide epitaxial layer formed on a front surface of an n+-type silicon carbide semiconductor substrate; a p-type layer becoming a channel region; a trench formed so as to be in contact with a p-type layer and having an oxide film and a gate electrode embedded therein; a p+-type layer arranged beneath the trench and between trenches; an n−-type layer in contact with the p-type layer, a p+-type layer, and the trench, and arranged in contact with a p+-type layer or on a surface side of the semiconductor substrate; an n-type layer in contact with the n−-type silicon carbide epitaxial layer and the p+-type layer, and having an impurity concentration higher than that of the n−-type layer and that of the n−-type silicon carbide epitaxial layer.