SiC V-Groove Power Transistor Structure to Minimize Miller Effect
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Solution Overview
Problem
Traditional V-groove N-MOSFETs suffer from high Cgd capacitance, leading to transient losses and potential device failure during switching operations due to the Miller effect, which complicates achieving both low specific on-resistance and high threshold voltage simultaneously.
Innovation Solution
The design incorporates a silicon carbide semiconductor power transistor with V-grooves, where the second well regions and pick-up regions are in contact with equal potential contacts on the top of the drift layer, converting the original Cgd capacitance to Cgs, thereby reducing the side effects of high Cgd capacitance by forming a drain-source capacitance and minimizing the Miller effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If nitridation process is used after gate oxidation to reduce channel resistance, then channel mobility is improved, but threshold voltage becomes lower instead of high
Solution Approach 1:
The patent changes the crystal orientation parameter from conventional (001) or (110) to (03-38) plane, which fundamentally alters the electrical characteristics of the SiC MOSFET. This parameter change enables simultaneous achievement of high channel mobility and high threshold voltage, resolving the contradiction between speed and reliability that plagues conventional devices.
2Area of stationary object
If V-grooves structure is used in SiC MOSFET, then device area is reduced and integration is improved, but Cgd capacitance increases due to direct connection between drain region and backside
Solution Approach 1:
The patent introduces an intermediary shielding structure (conductive layer or doped region) between the drain region and the backside contact in V-groove SiC MOSFETs. This intermediary element blocks the direct capacitive coupling that causes high Cgd, thereby reducing the harmful capacitance effect while preserving the area benefits of the V-groove structure.
Solution Approach 2:
The patent addresses the Cgd capacitance issue by moving the shielding function to a different spatial dimension - implementing it as a lateral conductive barrier or doped region within the V-groove structure rather than relying solely on vertical separation. This dimensional approach effectively reduces the capacitive coupling path.
Data Source
AI summary
A silicon carbide semiconductor power transistor and a method of manufacturing the same. The silicon carbide semiconductor power transistor of the disclosure includes a substrate made of silicon carbide (SiC), a drift layer disposed on the substrate, a gate layer formed on the drift layer, a plurality of first and second well pick-up regions disposed in the drift layer, a plurality of source electrodes, and a plurality of contacts. A plurality of V-grooves is formed in the drift layer. A first opening is formed in the gate layer at a bottom of each of the V-grooves, and a second opening is formed in the gate layer at a top of the drift layer between the V-grooves. The plurality of contacts is disposed inside the second opening to be in direct contact with the second well pick-up regions.