Stepped SiC VDMOSFET Well Structure for Short-Circuit Robustness
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional SiC VDMOSFETs have a relatively short short circuit withstand time (SCWT), which weakens the robustness of the power semiconductor device.
Innovation Solution
A power semiconductor device with a stepped second conductivity type well is designed, featuring a second conductivity type second-first well and a second conductivity type second-second well, where the width of the second-second well is controlled to be smaller than that of the second-first well, enhancing the SCWT characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a shallow P-well structure is used for ease of fabrication, then manufacturing complexity is reduced, but short circuit withstand time (SCWT) becomes short, weakening device robustness
Solution Approach 1:
The P-well structure is segmented into multiple regions with different depths and doping concentrations. The first P-well region has a first depth and doping concentration, while the second P-well region has a second depth greater than the first depth and a second doping concentration lower than the first. This segmentation allows the device to achieve both ease of fabrication and improved SCWT characteristics by creating optimized electrical fields in different regions.
Solution Approach 2:
Different regions of the P-well structure are assigned different local properties: the first P-well region has higher doping concentration for easier fabrication and basic functionality, while the second P-well region has lower doping concentration and greater depth for enhanced short circuit withstand time. This local quality differentiation resolves the contradiction between manufacturing ease and device robustness.
2Reliability
If a deep P-well structure is used to increase short circuit withstand time, then device robustness is improved, but junction field effect transistor (JFET) resistance increases
Solution Approach 1:
The P-well is divided into two segmented regions where the first region provides the necessary depth for improved SCWT, while the second region with higher doping concentration compensates for JFET resistance increases. This segmentation allows independent optimization of each region's properties to address different performance requirements simultaneously.
Solution Approach 2:
The doping concentration parameter is changed across different P-well regions: the first P-well region has a first doping concentration optimized for reducing JFET resistance, while the second P-well region has a second doping concentration lower than the first, optimized for increasing short circuit withstand time. This parameter variation resolves the contradiction between JFET resistance and SCWT.
Data Source
AI summary
A power semiconductor device, a power semiconductor module including the same, a power converter, and methods of manufacture are provided. The power semiconductor device can include a substrate, a first conductivity type epitaxial layer disposed on the substrate, and a stepped well structure, where the width of a lower region of the stepped well structure is narrower than an upper region, but wider than an insulating or trench region.