SiC Vertical Conduction Transistor Tapered Sidewall Design

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Solution Overview

Problem

Silicon-based semiconductor switches face limitations in reducing losses, increasing performance, and improving thermal management due to intrinsic electrical breakdown strength, ON-resistance, and thermal conductivity, necessitating the exploration of new materials and device structures for next-generation power converters.

Innovation Solution

The development of a vertical conduction junction transistor with a multilayered semiconductor unit cell using a silicon carbide (SiC) substrate, featuring an epitaxial drift layer, epitaxial channel layer, and a gate region with a tapered sidewall, which enhances switching speed, breakdown voltage, and thermal management through a trapezoidal channel control region and separate drift region for improved control of switching characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If silicon-based semiconductor switches are used, then the device can be manufactured with existing technology, but the breakdown voltage capability and thermal conductivity are fundamentally limited

Engineering Contradiction:
ImprovemanufacturabilityVSAvoidbreakdown voltage capability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent changes the material parameter from silicon to silicon carbide (SiC), which fundamentally alters the electrical and thermal properties. SiC enables higher breakdown voltage capability and improved thermal conductivity while maintaining compatibility with existing semiconductor manufacturing processes through epitaxial growth techniques.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent employs a multilayered composite structure consisting of different SiC layers with varying doping concentrations and compositions. This includes a drift layer, channel layer, and buffer layer, each optimized for specific functions while working together to achieve high breakdown voltage and low on-resistance.

Inventive Principle:
Principle #40Composite materials

2Speed

If the device size is reduced to improve power density, then the switching speed increases, but the breakdown voltage capability decreases due to silicon material limits

Engineering Contradiction:
Improveswitching speedVSAvoidbreakdown voltage capability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

By transitioning to SiC material, the patent enables smaller device dimensions to achieve the same breakdown voltage capability as larger silicon devices. The superior electrical properties of SiC allow for reduced drift layer thickness and shorter channel lengths, directly improving switching speed while maintaining voltage blocking capability.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If the drift layer thickness is increased to improve breakdown voltage, then the breakdown voltage capability increases, but the ON-resistance increases

Engineering Contradiction:
Improvebreakdown voltage capabilityVSAvoidON-resistance
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent applies local quality by creating a drift layer with a graded doping profile, where the doping concentration varies through the thickness of the layer. This allows different regions of the drift layer to be optimized for different functions: lower doping near the high-voltage terminal for breakdown voltage capability, and higher doping near the channel for reduced ON-resistance.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the doping concentration parameter through the drift layer thickness, creating an optimized profile that balances breakdown voltage and ON-resistance. This parameter variation allows the drift layer to simultaneously achieve high voltage blocking capability and low conduction losses.

Inventive Principle:
Principle #35Parameter changes

4Area of stationary object

If a vertical conduction structure is used to reduce device area, then the power density increases, but the manufacturing precision requirements increase

Engineering Contradiction:
Improvedevice areaVSAvoidlayer formation precision
Core Design Contradiction:
Area of stationary objectVSManufacturing precision

Solution Approach 1:

The patent employs preliminary action by using epitaxial growth to pre-form the complex multilayered SiC structure with precise thickness and doping profiles before any lithography or patterning steps. This establishes the vertical architecture early in the process, reducing subsequent manufacturing complexity and precision requirements.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration results in reduced ON-state resistance, lower gate capacitance, and higher frequency operation, enabling more efficient power conversion and improved thermal dissipation, thus overcoming the limitations of silicon-based switches.

Implementation Method 1

a vertical direction of the multilayered semiconductor unit cell is perpendicular to a top surface of the substrate

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Implementation Method 2

The gate region is formed in the sidewall of the epitaxial channel layer, the gate region having an inner gate region boundary that is parallel to the sidewall

Methodology Applied
Scientific EffectElectric field effect: Electric Field

Implementation Method 3

improved thermal management of the device

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS10276667B1High voltage breakdown tapered vertical conduction junction transistor
Publication Date: 2019.04.30 SILANNA ASIA
  • US10276667B1 patent drawing
  • US10276667B1 patent drawing
  • US10276667B1 patent drawing

AI summary

A vertical conduction junction transistor apparatus includes a multilayered semiconductor unit cell that has a substrate, epitaxial drift layer, epitaxial channel layer, gate region and channel control region. The substrate is silicon carbide (SiC). The epitaxial drift layer comprises SiC and is formed on the top surface of the substrate. The epitaxial channel layer comprises SiC and is formed on a top surface of the epitaxial drift layer, where a sidewall of the epitaxial channel layer is at an angle to the vertical direction. The gate region is formed in the sidewall of the epitaxial channel layer, the gate region having an inner gate region boundary that is parallel to the sidewall. The channel control region is in the epitaxial channel layer and has a width bounded by the inner gate region boundary. The channel control region has a trapezoidal cross-section in a plane taken in the vertical direction.