SiC VJFET Gate Bias for Minimized Current Flow Differences
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Solution Overview
Problem
Current silicon-based semiconductor devices for bidirectional power flow applications are limited by high switching and conduction losses, temperature limitations, and reliability issues, which hinder efficient operation in high-frequency and high-temperature conditions necessary for modern power conditioning systems.
Innovation Solution
The development of semiconductor devices with minimized current flow differences, specifically SiC VJFETs, utilizing a semiconductor stack with mesas and gates of different conductivity types, where the gates are formed to maximize drain current output by optimizing gate bias and increasing gate-to-gate spacing, thereby reducing resistance and maintaining voltage control below built-in potential values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If silicon-based semiconductor devices are used for bidirectional power flow, then device complexity is reduced and ease of manufacture is improved, but switching losses and conduction losses increase significantly
Solution Approach 1:
The patent changes the material parameter from silicon to wide-bandgap semiconductor (SiC, GaN), which fundamentally alters the electrical properties including bandgap energy, electron mobility, and thermal conductivity. This parameter change enables operation at higher frequencies and temperatures while reducing switching and conduction losses, directly resolving the energy loss issue despite increased manufacturing complexity
Solution Approach 2:
The patent employs composite material structures combining wide-bandgap semiconductor materials with specific device architectures (MESFET, HEMT, MODFET configurations). These composite structures integrate materials like SiC or GaN with carefully engineered layer compositions and doping profiles to optimize both electrical performance and manufacturability, balancing the contradiction between reduced losses and manufacturing ease
2Temperature
If silicon devices operate at higher temperatures, then power flow capability is improved, but reliability deteriorates due to temperature limitations
Solution Approach 1:
The patent exploits the fundamental material parameter change from silicon to wide-bandgap semiconductors, which have inherently higher breakdown electric fields and higher thermal stability. This allows the devices to operate reliably at temperatures above 200°C where silicon devices would fail, directly resolving the temperature-reliability contradiction by changing the base material properties
Solution Approach 2:
The patent designs the wide-bandgap semiconductor devices with inherent thermal management capabilities and robust gate structures that prevent catastrophic failure at high temperatures. The device architecture includes features like optimized gate lengths, doping profiles, and thermal conduction paths that cushion against thermal stress before it can cause reliability issues, enabling sustained high-temperature operation
3Manufacturing precision
If gate-to-gate spacing is increased to minimize current flow differences, then current symmetry is improved, but device area increases
Solution Approach 1:
The patent changes the channel conductivity type and optimizes the gate spacing parameter specifically for wide-bandgap materials. By adjusting the gate-to-gate spacing to values optimized for SiC or GaN characteristics rather than silicon, the patent achieves current symmetry with smaller increases in device area, as the different material physics allows for more compact spacing while maintaining performance
Solution Approach 2:
The patent applies different structural characteristics to different regions of the device, with optimized gate spacing and channel doping profiles in the bidirectional conduction regions. This local optimization allows current symmetry to be achieved in the critical bidirectional paths without unnecessarily increasing the overall device area, as other regions maintain compact dimensions
4Productivity
If operating frequency is increased to improve power flow efficiency, then system efficiency is improved, but switching losses in silicon devices increase
Solution Approach 1:
The patent exploits the fundamental parameter change in carrier mobility and switching characteristics of wide-bandgap materials. SiC and GaN devices have faster switching speeds and lower switching losses due to their material properties, enabling operation at higher frequencies (MHz range) without the prohibitive switching losses that limit silicon devices. This directly resolves the contradiction by changing the material parameters that govern switching behavior
Solution Approach 2:
The patent employs high-frequency periodic switching operation to achieve efficient power flow. By operating in the MHz frequency range enabled by wide-bandgap materials, the device performs rapid on-off cycling that improves power transfer efficiency while the inherent low switching losses of the wide-bandgap material prevent energy waste during each switching cycle, resolving the efficiency-loss contradiction
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the efficiency and reliability of bidirectional power flow by minimizing current flow differences, allowing SiC VJFETs to operate effectively at higher frequencies and temperatures with reduced switching losses and increased short-circuit hold-off time, thus improving system efficiency and reliability.
Implementation Method 1
a plurality of gates are formed to minimize current flow differences between a current flowing from the first layer to the plurality of mesas at a first applied gate bias and a current flowing from the first layer to the plurality of mesas at a second applied gate bias
Data Source
AI summary
A semiconductor device with minimized current flow differences and method of fabricating same are disclosed. The method includes forming a semiconductor stack including a plurality of layers that include a first layer having a first conductivity type and a second layer having a first conductivity type, in which the second layer is on top of the first layer, forming a plurality of mesas in the semiconductor layer stack, and forming a plurality of gates in the semiconductor layer stack having a second conductivity type and situated partially at a periphery of the mesas, in which the plurality of gates are formed to minimize current flow differences between a current flowing from the first layer to the plurality of mesas at a first applied gate bias and a current flowing from the first layer to the plurality of mesas at a second applied gate bias when voltage is applied to the semiconductor device.