SiC Epitaxial Wafer Defect Control for Forward Voltage Stability
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Solution Overview
Problem
SiC epitaxial wafers used in semiconductor devices suffer from VF deterioration due to the expansion of large-pit defects into stacking faults during forward conduction, leading to increased forward voltage.
Innovation Solution
A SiC epitaxial wafer with a total density of large-pit defects caused by micropipes and substrate carbon inclusions reduced to 1 defect/cm2 or less, achieved by selecting a high-quality SiC single crystal substrate and optimizing the epitaxial growth process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional SiC epitaxial wafers are used with standard defect densities, then manufacturing cost and production efficiency are maintained, but VF deterioration occurs due to expansion of large-pit defects into stacking faults during forward conduction
Solution Approach 1:
The patent applies preliminary action by selecting SiC single crystal substrates with pre-controlled low densities of micropipes and carbon inclusions before epitaxial growth. This preliminary selection ensures that the resulting epitaxial layer starts with minimal large-pit defect density (1 defect/cm² or less), preventing VF deterioration before it can occur during device operation.
Solution Approach 2:
The patent changes the critical parameter of large-pit defect density from conventional levels to an ultra-low threshold of 1 defect/cm² or less. This parameter change is achieved through stringent substrate selection criteria and optimized epitaxial growth conditions, fundamentally improving forward voltage stability in SiC devices.
2Reliability
If substrate quality is improved to reduce large-pit defects, then VF deterioration is suppressed, but substrate selection and manufacturing complexity increase
Solution Approach 1:
The patent replaces complex mechanical inspection and quality control processes with a defined parameter threshold system. By establishing a clear quantitative criterion (total density of micropipes and carbon inclusions ≤ 1 defect/cm²), the complex substrate selection process is simplified into a measurable and controllable parameter specification.
3Manufacturing precision
If epitaxial growth conditions are optimized to reduce large-pit defects, then stacking fault formation is minimized, but manufacturing process complexity increases
Solution Approach 1:
The patent optimizes epitaxial growth parameters including temperature, pressure, and gas composition to achieve ultra-low large-pit defect density. By carefully controlling these growth parameters, the process produces high-quality epitaxial layers with minimal defects while maintaining manufacturing feasibility through established CVD techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The reduced density of large-pit defects effectively suppresses VF deterioration, enhancing the reliability and performance of SiC devices by minimizing the formation of stacking faults during forward conduction.
Implementation Method 1
growing a SiC epitaxial layer (film) serving as an activated region of a device on a SiC single crystal substrate
Implementation Method 2
SiC bulk single crystal grown by sublimation recrystallization method
Implementation Method 3
obtained by being processed from SiC bulk single crystal grown by sublimation recrystallization method or the like, through chemical vapor deposition (CVD) or the like
Data Source
AI summary
A method of manufacturing a SiC epitaxial wafer in which a SiC epitaxial layer is formed on a SiC single crystal substrate, the method including identifying a total number of large-pit defects caused by micropipes in the SiC single crystal substrate and large-pit defects caused by substrate carbon inclusions, both of which are contained in the SiC epitaxial layer, using microscopic and photoluminescence images. Also disclosed is a method of manufacturing a SiC epitaxial wafer in which a SiC epitaxial layer is formed on a single crystal substrate, the method including identifying locations of the large-pit defects caused by micropipes in the SiC single crystal substrate and the large-pit defects caused by substrate carbon inclusions in the SiC epitaxial layer, using microscopic and photoluminescence images.