SiC Epitaxial Wafer Defect Reduction via Annealing and Graded Doping
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Solution Overview
Problem
Existing methods for manufacturing silicon carbide (SiC) epitaxial wafers face challenges such as high defect densities, particularly leakage current defects like carrot and triangular defects, which affect yield and electrical characteristics, and require lengthy processing times and inefficient gas use, limiting productivity and flexibility in device design.
Innovation Solution
A method involving annealing a tilted SiC bulk substrate in a reducing gas atmosphere at specific temperatures followed by temperature reduction and epitaxial growth at a lower temperature, using a heat treatment apparatus with a reducing gas system to minimize defects and enhance surface flatness without special pretreatment processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If epitaxial growth is performed at typical growth temperature of less than 1500 degrees C. to inhibit defect generation, then defect density is reduced, but manufacturing time increases and productivity decreases
Solution Approach 1:
The patent applies preliminary action by performing a defect inhibition layer growth process before the main epitaxial growth. This preliminary step prepares the substrate surface to prevent defect formation during subsequent high-temperature growth, allowing the main growth to proceed faster without generating defects. The defect inhibition layer is grown at lower temperature first, then the main layer is grown at higher temperature with reduced time.
2Manufacturing precision
If a defect inhibition layer is grown separately before the active layer, then defect density is reduced, but gas consumption increases and material gas use efficiency decreases
Solution Approach 1:
The patent merges the defect inhibition layer growth and active layer growth into a single continuous epitaxial growth process. By using a graded doping concentration profile that transitions from high to low doping levels, the process simultaneously forms both the defect inhibition layer and the active layer in one step, eliminating the need for separate growth processes and reducing overall gas consumption.
Solution Approach 2:
The patent applies parameter changes by continuously varying the doping concentration during the epitaxial growth process. The doping concentration is set to be higher at the beginning of growth (forming defect inhibition layer) and gradually decreased during subsequent growth (forming active layer). This dynamic parameter adjustment allows one growth process to achieve what previously required two separate processes.
3Ease of manufacture
If epitaxial growth is performed on a substrate tilted no more than 5 degrees from c-face to reduce raw material cost, then manufacturing cost is reduced, but step bunching occurs and electrical conductivity uniformity decreases
Solution Approach 1:
The patent applies local quality by creating a graded doping concentration profile within the epitaxial layer. The doping concentration is locally adjusted to be higher near the substrate interface and gradually decreased toward the surface. This local variation in doping concentration compensates for the step bunching effect caused by substrate tilt, maintaining electrical conductivity uniformity while allowing the use of cost-effective tilted substrates.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in SiC epitaxial wafers with significantly reduced defect densities, improved electrical characteristics, and increased productivity by shortening manufacturing time while maintaining efficient gas use, thereby enhancing the yield and flexibility of semiconductor devices.
Implementation Method 1
annealing a silicon carbide bulk substrate that is tilted less than 5 degrees from c-face, in an atmosphere containing a reducing gas at a first temperature T1 for a treatment time t
Implementation Method 2
performing epitaxial growth at a second temperature T2 below the annealing temperature T1 in the first step, while supplying a gas that contains at least a gas including silicon atoms and a gas including carbon atoms
Implementation Method 3
epitaxial growth of a semiconductor device active area in advance on a SiC bulk substrate with a thermal CVD method (thermal-chemical vapor deposition method)
Data Source
AI summary
A method is provided in order to manufacture a silicon carbide epitaxial wafer whose surface flatness is very good and has a very low density of carrot defects and triangular defects arising after epitaxial growth. The silicon carbide epitaxial wafer is manufactured by a first step of annealing a silicon carbide bulk substrate that is tilted less than 5 degrees from <0001> face, in a reducing gas atmosphere at a first temperature T1 for a treatment time t, a second step of reducing the temperature of the substrate in the reducing gas atmosphere, and a third step of performing epitaxial growth at a second temperature T2 below the annealing temperature T1 in the first step, while supplying at least a gas including silicon atoms and a gas including carbon atoms.