SiC Wafer Warpage Reduction via Dislocation Stress Relaxation

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

SiC wafers with larger sizes are prone to warping, which can lead to poor sensor detection, poor suction, and adverse effects on the semiconductor device process.

Innovation Solution

The SiC wafer is designed with a crystal surface having an offset angle of 0.5° or more and 10° or less in a specific direction, and dislocations are strategically introduced to relax stress and reduce warpage, with a higher density of first dislocations at certain measurement points.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the SiC wafer size is increased, then the productivity and device performance are improved, but the wafer is more likely to warp

Engineering Contradiction:
Improvewafer sizeVSAvoidwafer warpage
Core Design Contradiction:
ProductivityVSShape

Solution Approach 1:

The invention changes the physical-chemical parameters of the wafer by controlling dislocation density and introducing specific crystal defects. By adjusting the dislocation density to 1×10^6 to 1×10^8 cm^-2 and controlling the offset angle between crystal surfaces, the internal stress distribution is modified to reduce warpage in large-sized wafers

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The invention converts the harmful effect of dislocations (which typically cause device defects) into a beneficial effect by utilizing them for stress relaxation. By intentionally maintaining a controlled density of dislocations, the wafer's internal stress is relieved, preventing warpage while the dislocation density is kept within ranges that do not cause device killer defects

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

2Reliability

If dislocations are reduced to improve device reliability, then device killer defects are minimized, but stress relaxation is insufficient causing increased warpage

Engineering Contradiction:
Improvedevice reliabilityVSAvoidwafer warpage
Core Design Contradiction:
ReliabilityVSShape

Solution Approach 1:

The invention applies local quality by creating non-uniform dislocation distribution across the wafer. The dislocation density is controlled to be higher in specific regions (1×10^6 to 1×10^8 cm^-2) where stress relaxation is needed, while maintaining lower densities in device fabrication regions. This localized control allows stress relief without introducing device killer defects in critical areas

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The invention changes the parameter of dislocation density from the conventional approach of minimizing it uniformly across the entire wafer, to a controlled non-uniform distribution. By setting specific density ranges in different regions and controlling the offset angle between crystal surfaces, the invention achieves both stress relaxation and device reliability

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in SiC wafers with reduced warpage and minimal adverse effects on devices, improving the reliability and quality of semiconductor devices.

Implementation Method 1

dislocations can cause defects, they also play a role in relaxing stress that causes warping

Methodology Applied
Scientific EffectStress relaxation: Stress Relaxation

Implementation Method 2

when a first measurement point is measured using X-ray reflection topography with (3-3016) as a diffraction surface, dislocations are confirmed

Methodology Applied
Scientific EffectX-ray diffraction: X-Ray

Data Source

PatentUS20250154684A1SiC WAFER AND SiC EPITAXIAL WAFER
Publication Date: 2025.05.15 RESONAC CORP
  • US20250154684A1 patent drawing
  • US20250154684A1 patent drawing
  • US20250154684A1 patent drawing

AI summary

In a SiC wafer, a crystal surface has an offset angle of 0.5°-10° in a first direction with respect to a surface of the SiC wafer, dislocations are confirmed when a first measurement point is confirmed through X-ray reflection topography using (3-3016) as a diffraction surface, the first measurement point is a point shifted by a length of ½ of a radius of the SiC wafer in the first direction from the center of a measurement region that is 5 mm or more inside from the outer circumferential end of the SiC wafer, the dislocations include first dislocations having an aspect ratio of 5 or more and second dislocations having an aspect ratio of less than 3, where the aspect ratio is obtained by the specific method disclosed, and at the first measurement point, the density of the first dislocations is higher than the density of the second dislocations.