SiC Wafer Warp and TTV Control via Double-Sided Lapping
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Solution Overview
Problem
Existing methods for producing silicon carbide wafers often result in significant warp, bow, and total thickness variations (TTV), which can lead to uneven thermal contact and increased risk of wafer cracking during epitaxial growth and device fabrication, limiting the quality and reliability of silicon carbide semiconductor devices.
Innovation Solution
A method for forming high-quality silicon carbide wafers with improved warp, bow, and TTV by using a seeded sublimation growth process, followed by precise slicing and lapping techniques, including the use of a double-side lapping machine with controlled down force and subsequent polishing and etching to minimize defects, resulting in wafers with dimensions such as a diameter of at least 75 millimeters, warp less than 0.5 µm, bow less than 0.5 µm, and TTV less than 1.0 µm.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional slicing and lapping techniques are used to produce silicon carbide wafers, then manufacturing simplicity is maintained, but warp, bow, and TTV increase leading to poor wafer quality
Solution Approach 1:
The patent applies preliminary action by performing double-sided lapping where both sides of the wafer are lapped simultaneously to achieve uniform thickness and flatness. The first side is lapped to a predetermined thickness, then the wafer is flipped and the second side is lapped to match thickness, proactively preventing warp and bow before they affect downstream processes.
Solution Approach 2:
The lapping process is segmented into distinct stages: first side lapping to predetermined thickness, flipping the wafer, and second side lapping to match thickness. This segmentation allows precise control over each surface independently, enabling achievement of low warp, bow, and TTV specifications.
2Manufacturing precision
If wafer thickness and flatness are not precisely controlled, then manufacturing time is reduced, but work damage layers develop deeply into the wafer interior
Solution Approach 1:
The double-sided lapping process performs preliminary thickness adjustment on both surfaces, removing work damage layers deeply from the interior by ensuring uniform material removal. This preliminary action prevents the need for additional corrective processing steps later.
Solution Approach 2:
The patent replaces conventional single-sided mechanical lapping with a double-sided lapping system that simultaneously processes both wafer surfaces, achieving uniform thickness control and eliminating the need for multiple sequential operations that would increase processing time.
3Productivity
If large diameter silicon carbide wafers are produced, then productivity increases, but achieving low defect levels becomes more difficult
Solution Approach 1:
The double-sided lapping process applies preliminary action to large diameter wafers by simultaneously processing both surfaces to achieve uniform thickness and flatness across the entire wafer area, enabling production of 75mm and larger wafers with low defect levels.
Solution Approach 2:
The patent changes the lapping parameters by implementing double-sided simultaneous processing with controlled down forces and rotation speeds, adjusting these parameters to achieve uniform material removal across large diameter wafers while maintaining low defect levels.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method produces silicon carbide wafers with reduced warp, bow, and TTV, enhancing the crystal quality and performance of semiconductor devices, particularly in epitaxial growth processes, and enabling the fabrication of higher power and higher current devices with lower defect levels.
Implementation Method 1
the seed crystal and a source powder are both placed in a reaction crucible which is heated to the sublimation temperature of the source and in a manner that produces a thermal gradient between the source and the marginally cooler seed crystal. The thermal gradient encourages vapor phase movement of the materials from the source to the seed followed by condensation upon the seed and the resulting bulk crystal growth.
Implementation Method 2
The thermal gradient encourages vapor phase movement of the materials from the source to the seed followed by condensation upon the seed and the resulting bulk crystal growth.
Implementation Method 3
a double-side lapping machine is used to lap the sliced wafer. During rotation and revolution, the wafers 2 are ground with the abrasives.
Data Source
Figure 1a~1b
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Figure 4
AI summary
A high quality single crystal wafer of SiC is disclosed. The wafer has a diameter of at least about 3 inches, a warp of less than about 5 µm, a bow less than about 5 µm, and a total thickness variation of less than about 2.0 µm.