SiC Epitaxial Wafer Edge Defect Reduction via Segmented Polishing
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Solution Overview
Problem
The existing methods for manufacturing SiC epitaxial wafers fail to effectively reduce edge defects near the outer circumferential edge on the starting side of step-flow growth, which hinders the reduction of edge exclusion width and affects the yield and reliability of SiC devices.
Innovation Solution
A method involving rough polishing followed by final polishing, specifically using helical scan grinding with an inclined polishing grindstone, to minimize damage and reduce edge defects on the SiC single crystal substrate before forming the epitaxial layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional polishing methods are used on the outer circumferential edge, then manufacturing process is simple, but edge defects occur intensively
Solution Approach 1:
The polishing process is segmented into two distinct stages: rough polishing to remove damaged portions and restore the outer circumferential edge, followed by final polishing to achieve the desired surface finish. This segmentation allows each stage to be optimized independently, effectively reducing edge defects while maintaining process manageability.
Solution Approach 2:
Rough polishing is performed as a preliminary action before final polishing to remove damaged portions and restore the outer circumferential edge. This preliminary restoration eliminates the source of edge defects that would otherwise occur during subsequent epitaxial growth, preventing rather than merely treating the problem.
2Productivity
If edge exclusion width is reduced to increase effective area, then productivity increases, but edge defects become more critical
Solution Approach 1:
The rough polishing step applies preliminary anti-action by removing damaged portions and restoring the outer circumferential edge before epitaxial growth. This preventive measure counteracts the formation of edge defects that would otherwise compromise reliability when edge exclusion is minimized, enabling safe reduction of edge exclusion width.
3Manufacturing precision
If single polishing step is used, then manufacturing process is simple, but edge defects are not effectively reduced
Solution Approach 1:
The polishing process is divided into rough polishing and final polishing stages, each with specific objectives. Rough polishing focuses on removing damaged portions and restoring the edge, while final polishing achieves the required surface finish. This segmentation improves edge defect reduction effectiveness despite the increased process time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces edge defects, enhancing the effective area ratio for chip production and improving the yield of semiconductor chips by minimizing edge exclusion and preventing damage to the outer circumferential edge during the polishing process.
Implementation Method 1
a rough polishing step for subjecting an outer circumferential edge on the starting side of step-flow growth in the SiC single crystal substrate to rough polishing
Data Source
AI summary
In order to reduce edge defects efficiently and sufficiently, a method for manufacturing a SiC epitaxial wafer according to the present invention is a method for manufacturing a SiC epitaxial wafer that forms a SiC epitaxial layer on top of a SiC single crystal substrate having an off angle, and includes a rough polishing step for subjecting an outer circumferential edge on a starting side of step-flow growth in the SiC single crystal substrate to rough polishing before forming the SiC epitaxial layer; and a final polishing step for further polishing for finish.