Silicon Carbide Wafer Fault Layout for Stable Forward Voltage
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Solution Overview
Problem
Existing semiconductor devices using silicon carbide wafers face issues with stacking faults, particularly second stacking faults, which cause deterioration of forward voltage and increase in leakage current, leading to instability in device characteristics.
Innovation Solution
The wafer design incorporates a higher density of first stacking faults with specific geometric configurations that do not adversely affect characteristics, while reducing the density of second stacking faults, thereby stabilizing the crystal layer and suppressing stress and leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If second stacking faults are present in the silicon carbide crystal layer, then manufacturing is simpler, but forward voltage deteriorates and leakage current increases
Solution Approach 1:
The patent applies local quality by creating distinct regions with different stacking fault characteristics. First stacking faults are intentionally introduced at specific locations (at least 10^4 per cm^2) while suppressing second stacking faults. This spatial differentiation allows the crystal layer to have beneficial stress relief from first stacking faults while avoiding the harmful effects of second stacking faults on forward voltage and leakage current.
Solution Approach 2:
The patent changes the density parameter of stacking faults by introducing a minimum density requirement for first stacking faults (≥10^4 cm^-2) while maintaining second stacking faults below detection limits. This parameter control transforms the crystal layer from having random, harmful stacking faults to having controlled, beneficial first stacking faults that do not degrade device performance.
2Reliability
If stacking faults are reduced in the crystal layer, then device characteristics improve, but manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by introducing first stacking faults during the epitaxial growth process itself, rather than attempting to remove defects afterward. The stacking faults are incorporated into the crystal layer formation stage, allowing subsequent manufacturing steps to proceed without additional complexity while achieving the desired fault distribution that stabilizes forward voltage.
3Stability of the object's composition
If first stacking faults are introduced with specific density, then stress is suppressed and characteristics stabilize, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies self-service by allowing first stacking faults to form naturally during epitaxial growth under controlled conditions, where they automatically provide stress relief without requiring precise manual positioning. The faults serve their stress-suppression function based on their inherent formation mechanism rather than requiring exact placement, reducing the precision burden while achieving composition stability.
Data Source
AI summary
According to one embodiment, a wafer includes a base body including a first surface, and a crystal layer provided on the first surface. The crystal layer includes first stacking faults and one or second stacking faults. One of the first stacking faults includes a first long side, a first short side, and a first hypotenuse. A position of the first long side in a first direction from the base body to the crystal layer is between the base body in the first direction and a first corner portion in the first direction. One of the one or the plurality of second stacking faults includes a second long side, a second short side, and a second hypotenuse. A position of a second corner portion in the first direction is between the base body in the first direction and the second long side in the first direction.