SiC Wafer Flatness Control via Chemical Etching
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Solution Overview
Problem
The fabrication of silicon carbide (SiC) wafers is hindered by inefficient polishing processes due to its hard and chemically resistant nature, leading to high costs and slow material removal rates, which are not suitable for high-volume manufacturing and do not achieve the required flatness and smoothness for semiconductor device production.
Innovation Solution
A method involving large diameter lapping and polishing equipment to simultaneously control both local and global flatness of SiC wafers without the need for wafer etching, using diamond abrasives to achieve low roughness and thickness variations, followed by chemical mechanical polishing to prepare the surface for epitaxial deposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional polishing processes are used on SiC wafers, then the hard and chemically resistant nature of SiC is exploited, but the material removal rate is slow and costs are high
Solution Approach 1:
The patent replaces conventional mechanical polishing with a chemical etching process using KOH solution. The etching process exploits the crystallographic orientation dependence of SiC etching rates, allowing selective removal of material while achieving the required surface flatness and quality without the slow material removal rates associated with mechanical polishing of hard materials.
Solution Approach 2:
The patent changes the fundamental processing parameter from mechanical force to chemical reactivity. By using KOH etching at controlled temperatures and concentrations, the process achieves high material removal rates while maintaining surface quality through crystallographic selectivity, resolving the contradiction between productivity and reliability.
2Manufacturing precision
If multiple polishing steps are used to achieve required flatness and smoothness, then surface quality improves, but manufacturing time and cost increase
Solution Approach 1:
The patent replaces multiple sequential mechanical polishing steps with a single chemical etching process. The KOH etching process achieves the required flatness (less than 10 micrometers) and surface smoothness in one operation by exploiting anisotropic etching rates on different crystallographic planes, eliminating the need for multiple polishing stages.
Solution Approach 2:
The etching process operates continuously on the wafer surface, removing material uniformly across the entire surface area simultaneously. This continuous chemical action achieves the required precision faster than sequential mechanical polishing steps, reducing total manufacturing time while maintaining quality.
3Loss of substance
If conventional etching is applied to SiC, then material can be removed, but surface waviness increases requiring additional flattening processes
Solution Approach 1:
The patent applies local quality control through crystallographic orientation dependence. By controlling the wafer orientation and etching conditions, the process achieves selective etching rates on different crystallographic planes. This local variation in etching behavior naturally produces flat surfaces with minimal waviness, eliminating the need for additional flattening processes while maintaining high material removal efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method results in SiC wafers with superior global and local flatness and thickness performance, suitable for epitaxial growth, reducing manufacturing costs and enabling the production of high-quality semiconductor devices with large active areas.
Implementation Method 1
using diamond abrasives to achieve low roughness and thickness variations
Implementation Method 2
followed by chemical mechanical polishing to prepare the surface for epitaxial deposition
Implementation Method 3
the substrate will be placed into a chemical vapor deposition epitaxy process, which is used to grow crystalline thin films. As the thin film grows, it replicates the crystal structure presented on the substrate's surface
Data Source
Figure 1
AI summary
Methods for manufacturing silicon carbide wafers having superior specifications for bow, warp, total thickness variation (TTV), local thickness variation (LTV), and site front side least squares focal plane range (SFQR). The resulting SiC wafer has a mirror-like surface that is fit for epitaxial deposition of SiC. The specifications for bow, warp, total thickness variation (TTV), local thickness variation (LTV), and site front side least squares focal plane range (SFQR) of the wafer are preserved following the addition of the epitaxy layer.